Datasheet L6562 (STMicroelectronics) - 6
| Hersteller | STMicroelectronics |
| Beschreibung | Transition-Mode PFC Controller |
| Seiten / Seite | 16 / 6 — L6562. Figure 8. Feedback reference vs. T. Figure 11. Delay-to-output vs. … |
| Dokumentensprache | Englisch |
L6562. Figure 8. Feedback reference vs. T. Figure 11. Delay-to-output vs. T. Figure 9. OVP current vs. T
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L6562 Figure 8. Feedback reference vs. T
j
Figure 11. Delay-to-output vs. T
j VREF 2.6 tD(H-L) 500 (V) (ns) Vcc = 12 V Vcc = 12 V 400 2.55 300 2.5 200 2.45 100 2.4 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
Figure 9. OVP current vs. T
j
Figure 12. Multiplier characteristic
IOVP V 41 COMP V (pin 2) CS (pin 4) (µA) (V) (V) upper voltage Vcc = 12 V clamp 1.6 3.5 5.0 40.5 1.4 .5 4 4.0 1.2 3.2 40 1.0 0.8 3.0 0.6 39.5 0.4 2.8 0.2 39 2.6 -50 0 50 100 150 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Tj (°C) VMULT (pin 3) (V)
Figure 10. E/A output clamp levels vs. T
j
Figure 13. Multiplier gain vs. T
j Vpin2 K 1 (V) 6 Vcc = 12 V Upper clamp 0.8 VCOMP =4 V 5 Vcc = 12 V VMULT =1V 0.6 4 0.4 3 0.2 Lower clamp 2 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) 6/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History
j
Figure 11. Delay-to-output vs. T
j VREF 2.6 tD(H-L) 500 (V) (ns) Vcc = 12 V Vcc = 12 V 400 2.55 300 2.5 200 2.45 100 2.4 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
Figure 9. OVP current vs. T
j
Figure 12. Multiplier characteristic
IOVP V 41 COMP V (pin 2) CS (pin 4) (µA) (V) (V) upper voltage Vcc = 12 V clamp 1.6 3.5 5.0 40.5 1.4 .5 4 4.0 1.2 3.2 40 1.0 0.8 3.0 0.6 39.5 0.4 2.8 0.2 39 2.6 -50 0 50 100 150 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Tj (°C) VMULT (pin 3) (V)
Figure 10. E/A output clamp levels vs. T
j
Figure 13. Multiplier gain vs. T
j Vpin2 K 1 (V) 6 Vcc = 12 V Upper clamp 0.8 VCOMP =4 V 5 Vcc = 12 V VMULT =1V 0.6 4 0.4 3 0.2 Lower clamp 2 0 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C) 6/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History