Datasheet L6562 (STMicroelectronics) - 2

L6562 2 Description
(continued) The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25°C) internal voltage reference. The device features extremely low consumption (≤70 µA before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS- FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solu- tion for EN61000-3-2 compliant SMPS's up to 300W.
Table 2. Absolute Maximum Ratings Symbol Pin Parameter Value Unit
VCC 8 IC Supply voltage (Icc = 20 mA) self-limited V --- 1 to 4 Analog Inputs & Outputs -0.3 to 8 V IZCD 5 Zero Current Detector Max. Current -50 (source) mA 10 (sink) Ptot Power Dissipation @Tamb = 50°C (DIP-8) 1 W (SO-8) 0.65 Tj Junction Temperature Operating range -40 to 150 °C Tstg Storage Temperature -55 to 150 °C
Figure 3. Pin Connection
(Top view) INV 1 8 Vcc COMP 2 7 GD MULT 3 6 GND CS 4 5 ZCD
Table 3. Thermal Data Symbol Parameter SO8 Minidip Unit
Rth j-amb Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W 2/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History