Datasheet AD8343 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | DC-to-2.5 GHz High IP3 Active Mixer |
| Seiten / Seite | 32 / 7 — AD8343. SIMPLIFIED INTERFACE SCHEMATICS. VPOS. OUTP OUTM. 5VDC. LOIP. … |
| Dateiformat / Größe | PDF / 2.2 Mb |
| Dokumentensprache | Englisch |
AD8343. SIMPLIFIED INTERFACE SCHEMATICS. VPOS. OUTP OUTM. 5VDC. LOIP. LOIM. 1.2VDC. INPP. 25kΩ. PWDN. INPM. 1.2V. BIAS. CELL. 2VDC. DCPL. 10Ω. VBIAS. 360mVDC
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AD8343 SIMPLIFIED INTERFACE SCHEMATICS VPOS OUTP OUTM 5V 5V DC DC 5VDC LOIP VPOS LOIM 5VDC VPOS 1.2VDC 5V INPP DC 25kΩ PWDN INPM
3 5
1.2V
00
DC
4-
BIAS
-00 4 03
CELL
03 01 01 Figure 3. Input and Output Ports Figure 5. Power-Down Pin
2VDC DCPL BIAS VPOS VPOS CELL R1 5VDC 10Ω VBIAS 360mVDC 360mVDC LOIP LOIP TO LO MIXER BUFFER LOIM 360mVDC CORE
6
360mVDC LOIM 400Ω 400Ω
04 00 -0 4- 34 03 10 01 0 Figure 4. LO Port Figure 6. Bias Decoupling Pin Rev. B | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BASIC OPERATING INSTRUCTIONS TYPICAL AC PERFORMANCE TYPICAL ISOLATION PERFORMANCE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVER CHARACTERISTICS TRANSMIT CHARACTERISTICS CIRCUIT DESCRIPTION DC INTERFACES BIASING AND DECOUPLING (VPOS, DCPL) POWER-DOWN INTERFACE (PWDN) AC INTERFACES INPUT INTERFACE (INPP AND INPM) SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION INPUT MATCHING CONSIDERATIONS INPUT BIASING CONSIDERATIONS OUTPUT INTERFACE (OUTP, OUTM) OUTPUT MATCHING CONSIDERATIONS OUTPUT BIASING CONSIDERATIONS INPUT AND OUTPUT STABILITY CONSIDERATIONS LOCAL OSCILLATOR INPUT INTERFACE (LOIP, LOIM) DC COUPLING THE LO A STEP-BY-STEP APPROACH TO IMPEDANCE MATCHING Circuit Setup Establish Target Impedance Measure AD8343 Differential Impedance at Location of First Matching Component Design the Matching Network Transfer the Matching Network to the Final Design APPLICATIONS DOWNCONVERTING MIXER UPCONVERTING MIXER EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
3 5
1.2V
00
DC
4-
BIAS
-00 4 03
CELL
03 01 01 Figure 3. Input and Output Ports Figure 5. Power-Down Pin
2VDC DCPL BIAS VPOS VPOS CELL R1 5VDC 10Ω VBIAS 360mVDC 360mVDC LOIP LOIP TO LO MIXER BUFFER LOIM 360mVDC CORE
6
360mVDC LOIM 400Ω 400Ω
04 00 -0 4- 34 03 10 01 0 Figure 4. LO Port Figure 6. Bias Decoupling Pin Rev. B | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BASIC OPERATING INSTRUCTIONS TYPICAL AC PERFORMANCE TYPICAL ISOLATION PERFORMANCE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVER CHARACTERISTICS TRANSMIT CHARACTERISTICS CIRCUIT DESCRIPTION DC INTERFACES BIASING AND DECOUPLING (VPOS, DCPL) POWER-DOWN INTERFACE (PWDN) AC INTERFACES INPUT INTERFACE (INPP AND INPM) SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION INPUT MATCHING CONSIDERATIONS INPUT BIASING CONSIDERATIONS OUTPUT INTERFACE (OUTP, OUTM) OUTPUT MATCHING CONSIDERATIONS OUTPUT BIASING CONSIDERATIONS INPUT AND OUTPUT STABILITY CONSIDERATIONS LOCAL OSCILLATOR INPUT INTERFACE (LOIP, LOIM) DC COUPLING THE LO A STEP-BY-STEP APPROACH TO IMPEDANCE MATCHING Circuit Setup Establish Target Impedance Measure AD8343 Differential Impedance at Location of First Matching Component Design the Matching Network Transfer the Matching Network to the Final Design APPLICATIONS DOWNCONVERTING MIXER UPCONVERTING MIXER EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE