Datasheet PEMD12, PUMD12 (Nexperia) - 4

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NXP Semiconductors PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k , R2 = 47 k 5. Limiting values Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity
VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage TR1 positive - +40 V negative - 10 V input voltage TR2 positive - +10 V negative - 40 V IO output current - 100 mA ICM peak collector current single pulse; - 100 mA t  p 1 ms P  tot total power dissipation Tamb 25 C PEMD12 (SOT666) [1][2] - 200 mW PUMD12 (SOT363) [1] - 200 mW
Per device
P  tot total power dissipation Tamb 25 C PEMD12 (SOT666) [1][2] - 300 mW PUMD12 (SOT363) [1] - 300 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 21 November 2011 3 of 16
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Thermal characteristics 7. Characteristics 8. Test information 8.1 Quality information 9. Package outline 10. Packing information 11. Soldering 12. Revision history 13. Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers 13.4 Trademarks 14. Contact information 15. Contents