Datasheet MAX6846, MAX6847, MAX6848, MAX6849 (Maxim) - 3

Low-Power, Adjustable Battery Monitors with Hysteresis and Integrated µP Reset MAX6846–MAX6849 ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.6V to 5.5V, VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LBO, LBOL, LBOH Output Output deasserted 500 nA Open-Drain Leakage Current MAX68_ _ _ _ T 3.000 3.075 3.150 MAX68_ _ _ _ S 2.850 2.925 3.000 MAX68_ _ _ _ R 2.550 2.625 2.700 VCC Reset Threshold VTH MAX68_ _ _ _ Z 2.250 2.313 2.375 V MAX68_ _ _ _ Y 2.125 2.188 2.250 MAX68_ _ _ _ W 1.620 1.665 1.710 MAX68_ _ _ _ V 1.530 1.575 1.620 VCC Reset Hysteresis 0.3 % V V CC falling at 10mV/µs from (VTH + 100mV) CC to RESET Delay tRD 50 µs to (VTH - 100mV) MAX68_ _ _ _ _ D3 150 225 300 VCC to RESET Timeout Period tRP ms MAX68_ _ _ _ _ D7 1200 1800 2400 VIL 0.3 x VCC MR Input Voltage V VIH 0.7 x VCC MR Minimum Pulse Width tMPW 1 µs MR Glitch Rejection 100 ns MR to RESET Delay 200 ns MR Reset Timeout Period tMRP 150 225 300 ms MR Pullup Resistance MR to VCC 750 1500 2250 Ω MR Rising Debounce Period tDEB (Note 3) 150 225 300 ms VCC ≥ 1.53V, ISOURCE = 100µA, RESET 0.8 x VCC deasserted RESET Output High VOH V (Push-Pull) VCC ≥ 2.55V, ISOURCE = 500µA, RESET 0.8 x VCC deasserted VCC ≥ 1.0V, ISINK = 50µA, RESET asserted 0.3 VCC ≥ 1.2V, ISINK = 100µA, RESET asserted 0.3 RESET Output Low VOL V VCC ≥ 2.12V, ISINK = 1.2mA, RESET 0.3 asserted RESET Output Leakage Current RESET deasserted 500 nA (Open Drain)
Note 1:
Production testing done at TA = +25°C; limits over temperature guaranteed by design only.
Note 2:
The device is powered up by the highest voltage between VDD and VCC.
Note 3:
MR input ignores falling input pulses, which occur within the MR debounce period (tDEB) after a valid MR reset assertion. This prevents invalid reset assertion due to switch bounce.
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