Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 9

eGaN® FET DATASHEET
EPC23102
Gate Driver SW Node Switching Transients
The EPC23102 IC integrates both HS and LS FET gate drivers with very low The switching rate and transients at the output node, SW, is control ed impedance (0.4 Ω) and high pulse current (5 A) push-pull NFET output stage. by application topologies resulting in hard or soft switching transitions. Figure 10 is the simplified circuit diagram of the gate driver output stage. The more stressful hard switching transition needs to be control ed by a combination of tuning gate drive turn-on and turn-off circuits for the
Figure 10: Simplified Circuit Diagram of Gate Driver Output
HS FET (Q1) and LS FET (Q2) and minimizing the power loop parasitic
Stage
inductances. VDD The on-chip gate drive buffers practical y eliminate effects of common source inductance and gate drive loop inductance. Switching times are Internal tuned by external resistors, RDRV and RBOOT , as shown in Figure 12 to Bootstrap achieve SW switching rate of 10 to 50 V/ns spanning zero to full load Gate current. The choice of switching rates is dictated by efficiency versus Drive MPO EMI mitigation. C Q B1
Figure 12: Simplified circuit diagram of external tuning resistor, internal gate drivers and output FETs
A MSO MS1 VIN VBOOT The HS and LS gate drive voltage levels are derived from their respective internal low side (V R DD) and high side (VBOOT) power supplies. To ensure BOOT Internal that the gate drive level (Q) is sufficiently close to VDD or VBOOT, an internal Bootstrap MPO bootstrap circuit is used to turn-on M Gate PO. Here the MPO and MSO pair Drive HSG works similarly to the half-bridge power stage Q1 and Q2 output FETs C Q1 B1 except all the circuits are internal to the IC. CB1 is an internal bootstrap HGoff capacitor. The PWM inputs, HSIN and LSIN, are used as the clocks for their MS1 MSO respective high side and low side internal bootstrap gate drive circuit. SW As with any bootstrap circuit, the gate drive output cannot have 100% V duty cycle to al ow C DD B1 to be recharged. For the EPC23102 IC, the PWM input pulse width must not exceed a maximum of 200 µs on/off duration RDRV Internal and a minimum pulse width on/off duration of 20 ns as specified in the Bootstrap MPO Gate recommended operating condition table. At initial startup of the HS Drive LSG V IN DRV C Q2 and LS B1 IN clocking cycle, CB1 needs to be charged from zero. A delay of nominal y 6 switching cycles appears before the gate drive output wil LGoff fol ow the PWM input pulses. Figure 11a and 11b il ustrate the gate drive MS1 MSO PGND output switching behavior.
Figure 11a: Maximum and Minimum PWM Input Pulse Width On Figure 11b: Missing High Side and Low Side Gate pulses at startup or Off duration to refresh internal gate drive bootstrap circuit due to initial charging of internal gate drive bootstrap circuit
VBOOT
HSIN or LS
V
IN
DD On duration Off duration HSIN LSIN Maximum On or Off = 200 μs Minimum On or Off = 20 ns HGate LGate Missing pulses EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 9