Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 6
| Hersteller | Efficient Power Conversion |
| Beschreibung | ePower Stage IC |
| Seiten / Seite | 15 / 6 — eGaN® FET DATASHEET. Truth Table. VDD. VBOOT – VPHASE. HSIN. LSIN. HS … |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
eGaN® FET DATASHEET. Truth Table. VDD. VBOOT – VPHASE. HSIN. LSIN. HS FET. LS FET. Application Information. General Description
Modelllinie für dieses Datenblatt
Textversion des Dokuments
eGaN® FET DATASHEET
EPC23102
Truth Table VDD VBOOT – VPHASE HSIN LSIN HS FET LS FET
<POR – – – OFF OFF – 0 OFF OFF >POR <UVLO – 1 OFF ON 0 0 OFF OFF 0 1 OFF ON >POR >UVLO 1 0 ON OFF 1 1 OFF
Application Information General Description Figure 4: Functional Block Diagram
The EPC23102 ePowerTM Stage IC integrates a half-bridge gate driver with internal 4 CDD high side and low side FETs. Integration is implemented using EPC’s proprietary V 5 DRV VDD
High side
VBOOT 13 GaN IC technology. The monolithic chip integrates input logic interface, level C R UVLO BOOT 12 C DRV V Sync BOOT Enable IN shifting, bootstrap charging and gate drive boot VIN 10 logic VIN buffer circuits control ing high side and 3 EN Level Gate low side eGaN output FETs configured as driver C shift IN 150 k Logic a half-bridge power stage. Robust level + V GND PHASE 11 shifters from low side to high side channels POR SW 9 are designed to operate correctly with +
EPC23102
SW 1 HS soft and hard switching conditions even IN Cross- V R DD DRV 6 over VDRV at large negative clamped voltage and to LS LO Delay 2 IN match Gate avoid false trigger from fast dv/dt transients level driver including those driven by external sources shift 7 AGND PGND 8 or other phases. Internal circuits integrate PGND the functions of charging and disabling of the logic and bootstrap power supplies. Protection features are added to protect the output FETs from unwanted turn-on at low or even complete loss of supply voltages.
Figure 5: EPC23102 QFN package outline, pinouts and exposed backside of the GaN IC die
The single chip GaN IC is mounted inside a 3.5 x 5 mm Quad Flat No-lead (QFN) package using a flip chip on 10
Bottom
lead-frame technique. This packaging structure al ows 9 very low parasitic inductance from the power terminals 8 to the underlying PCB solder pads. The exposed QFN 11 1213 pads are designed to have at least 0.6 mm spacing between high and low voltage pins to meet IPC voltage
Top
creepage rule for 100 V. Another enhancement exposes 1 the backside of the Gan IC die on the top side of the 2 7 3 6 package while completely encapsulating the rest of the
EPC
4
23102
5 GaN IC die. This al ows a very low thermal resistance
CYYWWE 123456
path from the die junction to an attached heatsink Site/date code which in effect increase the al owable power dissipation Lot code and thus higher current handling capability. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 6
EPC23102
Truth Table VDD VBOOT – VPHASE HSIN LSIN HS FET LS FET
<POR – – – OFF OFF – 0 OFF OFF >POR <UVLO – 1 OFF ON 0 0 OFF OFF 0 1 OFF ON >POR >UVLO 1 0 ON OFF 1 1 OFF
Application Information General Description Figure 4: Functional Block Diagram
The EPC23102 ePowerTM Stage IC integrates a half-bridge gate driver with internal 4 CDD high side and low side FETs. Integration is implemented using EPC’s proprietary V 5 DRV VDD
High side
VBOOT 13 GaN IC technology. The monolithic chip integrates input logic interface, level C R UVLO BOOT 12 C DRV V Sync BOOT Enable IN shifting, bootstrap charging and gate drive boot VIN 10 logic VIN buffer circuits control ing high side and 3 EN Level Gate low side eGaN output FETs configured as driver C shift IN 150 k Logic a half-bridge power stage. Robust level + V GND PHASE 11 shifters from low side to high side channels POR SW 9 are designed to operate correctly with +
EPC23102
SW 1 HS soft and hard switching conditions even IN Cross- V R DD DRV 6 over VDRV at large negative clamped voltage and to LS LO Delay 2 IN match Gate avoid false trigger from fast dv/dt transients level driver including those driven by external sources shift 7 AGND PGND 8 or other phases. Internal circuits integrate PGND the functions of charging and disabling of the logic and bootstrap power supplies. Protection features are added to protect the output FETs from unwanted turn-on at low or even complete loss of supply voltages.
Figure 5: EPC23102 QFN package outline, pinouts and exposed backside of the GaN IC die
The single chip GaN IC is mounted inside a 3.5 x 5 mm Quad Flat No-lead (QFN) package using a flip chip on 10
Bottom
lead-frame technique. This packaging structure al ows 9 very low parasitic inductance from the power terminals 8 to the underlying PCB solder pads. The exposed QFN 11 1213 pads are designed to have at least 0.6 mm spacing between high and low voltage pins to meet IPC voltage
Top
creepage rule for 100 V. Another enhancement exposes 1 the backside of the Gan IC die on the top side of the 2 7 3 6 package while completely encapsulating the rest of the
EPC
4
23102
5 GaN IC die. This al ows a very low thermal resistance
CYYWWE 123456
path from the die junction to an attached heatsink Site/date code which in effect increase the al owable power dissipation Lot code and thus higher current handling capability. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 6