Datasheet AT89C51 (Microchip) - 3

AT89C51
The AT89C51 provides the following standard features: 4K Port 2 pins that are externally being pulled low will source bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit current (I ) because of the internal pullups. IL timer/counters, a five vector two-level interrupt architecture, Port 2 emits the high-order address byte during fetches a full duplex serial port, on-chip oscillator and clock cir- from external program memory and during accesses to cuitry. In addition, the AT89C51 is designed with static logic external data memory that use 16-bit addresses (MOVX @ for operation down to zero frequency and supports two DPTR). In this application, it uses strong internal pullups software selectable power saving modes. The Idle Mode when emitting 1s. During accesses to external data mem- stops the CPU while allowing the RAM, timer/counters, ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the serial port and interrupt system to continue functioning. The contents of the P2 Special Function Register. Power-down Mode saves the RAM contents but freezes Port 2 also receives the high-order address bits and some the oscillator disabling all other chip functions until the next control signals during Flash programming and verification. hardware reset.
Port 3 Pin Description
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.
VCC
When 1s are written to Port 3 pins they are pulled high by Supply voltage. the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
GND
current (IIL) because of the pullups. Ground. Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
Port Pin Alternate Functions
output port, each pin can sink eight TTL inputs. When 1s P3.0 RXD (serial input port) are written to port 0 pins, the pins can be used as high- P3.1 TXD (serial output port) impedance inputs. Port 0 may also be configured to be the multiplexed low- P3.2 INT0 (external interrupt 0) order address/data bus during accesses to external pro- P3.3 INT1 (external interrupt 1) gram and data memory. In this mode P0 has internal P3.4 T0 (timer 0 external input) pullups. Port 0 also receives the code bytes during Flash program- P3.5 T1 (timer 1 external input) m i ng , a nd o u tp u t s th e c o d e b y t e s du rin g p ro g ra m P3.6 WR (external data memory write strobe) verification. External pullups are required during program P3.7 RD (external data memory read strobe) verification.
Port 1
Port 3 also receives some control signals for Flash pro- gramming and verification. Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs.
RST
When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Reset input. A high on this pin for two machine cycles while Port 1 pins that are externally being pulled low will source the oscillator is running resets the device. current (I ) because of the internal pullups. IL
ALE/PROG
Port 1 also receives the low-order address bytes during Flash programming and verification. Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This
Port 2
pin is also the program pulse input (PROG) during Flash programming. Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. In normal operation ALE is emitted at a constant rate of 1/6 When 1s are written to Port 2 pins they are pulled high by the oscillator frequency, and may be used for external tim- the internal pullups and can be used as inputs. As inputs, ing or clocking purposes. Note, however, that one ALE
3
Document Outline Block Diagram Features Description Pin Description VCC GND Port 0 Port 1 Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Oscillator Characteristics Status of External Pins During Idle and Power-down Modes Lock Bit Protection Modes Programming the Flash Programming Interface Flash Programming Modes Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V) Flash Programming and Verification Characteristics Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information