Datasheet EFM8SB1 (Silicon Labs) - 6
| Hersteller | Silicon Labs |
| Beschreibung | EFM8 Sleepy Bee Family |
| Seiten / Seite | 71 / 6 — 3.2 Power. Table 3.1. Power Modes. Power Mode. Details. Mode Entry. … |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
3.2 Power. Table 3.1. Power Modes. Power Mode. Details. Mode Entry. Wake-Up Sources. Note:. 3.3 I/O. silabs.com
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link to page 6 EFM8SB1 Data Sheet System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi- ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Table 3.1. Power Modes Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — — Idle • Core halted Set IDLE bit in PCON0 Any interrupt • All peripherals clocked and fully operational • Code resumes execution on wake event Suspend • Core and digital peripherals halted 1. Switch SYSCLK to • RTC0 Alarm Event • Internal oscillators disabled HFOSC0 or LPOSC0 • RTC0 Fail Event • Code resumes execution on wake event 2. Set SUSPEND bit in • CS0 Interrupt PMU0CF • Port Match Event • Comparator 0 Rising Edge Stop • All internal power nets shut down Set STOP bit in PCON0 Any reset source • Pins retain state • Exit on any reset source Sleep1 • Most internal power nets shut down 1. Disable unused ana- • RTC0 Alarm Event • Select circuits remain powered log peripherals • RTC0 Fail Event • Pins retain state 2. Set SLEEP bit in • Port Match Event PMU0CF • All RAM and SFRs retain state • Comparator 0 Rising • Code resumes execution on wake event Edge
Note:
1. Entering Sleep may disconnect the active debug session.
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7. • Up to 17 multi-functions I/O pins, supporting digital and analog functions. • Flexible priority crossbar decoder for digital peripheral assignment. • Two drive strength settings for each pin. • Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1). • Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com
| Building a more connected world. Rev. 1.4 | 5 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi- ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Table 3.1. Power Modes Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational — — Idle • Core halted Set IDLE bit in PCON0 Any interrupt • All peripherals clocked and fully operational • Code resumes execution on wake event Suspend • Core and digital peripherals halted 1. Switch SYSCLK to • RTC0 Alarm Event • Internal oscillators disabled HFOSC0 or LPOSC0 • RTC0 Fail Event • Code resumes execution on wake event 2. Set SUSPEND bit in • CS0 Interrupt PMU0CF • Port Match Event • Comparator 0 Rising Edge Stop • All internal power nets shut down Set STOP bit in PCON0 Any reset source • Pins retain state • Exit on any reset source Sleep1 • Most internal power nets shut down 1. Disable unused ana- • RTC0 Alarm Event • Select circuits remain powered log peripherals • RTC0 Fail Event • Pins retain state 2. Set SLEEP bit in • Port Match Event PMU0CF • All RAM and SFRs retain state • Comparator 0 Rising • Code resumes execution on wake event Edge
Note:
1. Entering Sleep may disconnect the active debug session.
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7. • Up to 17 multi-functions I/O pins, supporting digital and analog functions. • Flexible priority crossbar decoder for digital peripheral assignment. • Two drive strength settings for each pin. • Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1). • Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com
| Building a more connected world. Rev. 1.4 | 5 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents