Datasheet MC74VHC04 (ON Semiconductor)
| Hersteller | ON Semiconductor |
| Beschreibung | Hex Inverter |
| Seiten / Seite | 7 / 1 — www.onsemi.com. MARKING DIAGRAMS. Features. SOIC−14. D SUFFIX. CASE 751A. … |
| Revision | 7 |
| Dateiformat / Größe | PDF / 245 Kb |
| Dokumentensprache | Englisch |
www.onsemi.com. MARKING DIAGRAMS. Features. SOIC−14. D SUFFIX. CASE 751A. TSSOP−14. DT SUFFIX. CASE 948G. FUNCTION TABLE. Inputs. Outputs
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Hex Inverter MC74VHC04 The MC74VHC04 is an advanced high speed CMOS inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer
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output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
MARKING DIAGRAMS
to 3 V systems. 14
Features
•
SOIC−14
High Speed: t VHC04G PD = 3.8 ns (Typ) at VCC = 5 V
D SUFFIX
AWLYWW • Low Power Dissipation: I
CASE 751A
CC = 2 mA (Max) at TA = 25°C 1 • High Noise Immunity: V 1 NIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs 14 • Balanced Propagation Delays
TSSOP−14
VHC • Designed for 2 V to 5.5 V Operating Range
DT SUFFIX
04 • ALYWG Low Noise: V
CASE 948G
OLP = 0.8 V (Max) 1 G • Pin and Function Compatible with Other Standard Logic Families 1 • Latchup Performance Exceeds 300 mA A = Assembly Location • ESD Performance: HBM > 2000 V; Machine Model > 200 V WL, L = Wafer Lot • Y = Year Chip Complexity: 36 FETs or 9 Equivalent Gates WW, W = Work Week • NLV Prefix for Automotive and Other Applications Requiring G or G = Pb−Free Package Unique Site and Control Change Requirements; AEC−Q100 (Note: Microdot may be in either location) Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant
FUNCTION TABLE Inputs Outputs
1 2 A1 Y1
A Y
14 1 A1 VCC L H 3 4 13 H L A2 Y2 2 Y1 A6 12 34567 A2 Y6 5 6 A3 Y3
ORDERING INFORMATION
11 Y = A Y2 A5
Device Package Shipping
† 9 8 A4 Y4 10 A3 Y5 MC74VHC04DR2G SOIC−14 2500 / Tape & (Pb−Free) Reel 9 11 10 Y3 A4 MC74VHC04DTR2G TSSOP−14 2500 / Tape & A5 Y5 (Pb−Free) Reel 8 GND Y4 NLV74VHC04DTR2G TSSOP−14 2500 / Tape & 13 12 A6 Y6 (Pb−Free) Reel
Figure 2. Pinout:
†For information on tape and reel specifications, including part orientation and tape sizes, please
Figure 1. Logic Diagram 14−Lead Packages
refer to our Tape and Reel Packaging Specification
(Top View)
Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2020 − Rev. 7 MC74VHC04/D
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output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
MARKING DIAGRAMS
to 3 V systems. 14
Features
•
SOIC−14
High Speed: t VHC04G PD = 3.8 ns (Typ) at VCC = 5 V
D SUFFIX
AWLYWW • Low Power Dissipation: I
CASE 751A
CC = 2 mA (Max) at TA = 25°C 1 • High Noise Immunity: V 1 NIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs 14 • Balanced Propagation Delays
TSSOP−14
VHC • Designed for 2 V to 5.5 V Operating Range
DT SUFFIX
04 • ALYWG Low Noise: V
CASE 948G
OLP = 0.8 V (Max) 1 G • Pin and Function Compatible with Other Standard Logic Families 1 • Latchup Performance Exceeds 300 mA A = Assembly Location • ESD Performance: HBM > 2000 V; Machine Model > 200 V WL, L = Wafer Lot • Y = Year Chip Complexity: 36 FETs or 9 Equivalent Gates WW, W = Work Week • NLV Prefix for Automotive and Other Applications Requiring G or G = Pb−Free Package Unique Site and Control Change Requirements; AEC−Q100 (Note: Microdot may be in either location) Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant
FUNCTION TABLE Inputs Outputs
1 2 A1 Y1
A Y
14 1 A1 VCC L H 3 4 13 H L A2 Y2 2 Y1 A6 12 34567 A2 Y6 5 6 A3 Y3
ORDERING INFORMATION
11 Y = A Y2 A5
Device Package Shipping
† 9 8 A4 Y4 10 A3 Y5 MC74VHC04DR2G SOIC−14 2500 / Tape & (Pb−Free) Reel 9 11 10 Y3 A4 MC74VHC04DTR2G TSSOP−14 2500 / Tape & A5 Y5 (Pb−Free) Reel 8 GND Y4 NLV74VHC04DTR2G TSSOP−14 2500 / Tape & 13 12 A6 Y6 (Pb−Free) Reel
Figure 2. Pinout:
†For information on tape and reel specifications, including part orientation and tape sizes, please
Figure 1. Logic Diagram 14−Lead Packages
refer to our Tape and Reel Packaging Specification
(Top View)
Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2020 − Rev. 7 MC74VHC04/D