Datasheet ADG511, ADG512, ADG513 (Analog Devices) - 8

ADG511/ADG512/ADG513 0.006
network RC and CC. This compensation network also reduces
VDD = +5V
the hold time glitch while optimizing the acquisition time. Using
VSS = –5V
the illustrated op amps and component values, the pedestal
0.004 I T D (ON) A = +25 C
error has a maximum value of 5 mV over the ± 3 V input range.
nA
The acquisition time is 2.5 µs while the settling time is 1.85 µs.
– 0.002 ID (OFF) +5V 0.000 IS (OFF) 2200pF +5V –0.002 SW2 +5V S D C LEAKAGE CURRENT C RC 1000pF OP07 VOUT VIN SW1 –0.004 75 AD845 S D CH 2200pF –5V –0.006 –5V –5 –4 –3 –2 –1 0 1 2 3 4 5 ADG511/ VD OR VS – DRAIN OR SOURCE VOLTAGE – V ADG512/ ADG513
TPC 7. Leakage Currents as a Function of VD (VS)
–5V
Figure 1. Accurate Sample-and-Hold
110 VDD = +5V VSS = –5V TRENCH ISOLATION 100
The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 2). When the NMOS and PMOS devices
dB – 90
are not electrically isolated from each other, there exists the possibility of “latch-up” caused by parasitic junctions between
80
CMOS transistors. Latch-up is caused when P-N junctions that
CROSSTALK
are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive.
70
CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMOS
60
transistors form a diode that is reverse biased under normal
100 1k 10k 100k 1M 10M FREQUENCY – Hz
operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR)- TPC 8. Crosstalk vs. Frequency type circuit is formed by the two transistors, causing a signifi- cant amplification of the current that, in turn, leads to latch-up.
APPLICATION
With Trench Isolation, this diode is removed; the result is a Figure 1 illustrates a precise sample-and-hold circuit. An AD845 latch-up-proof circuit. is used as the input buffer while the output operational ampli- fier is an OP07. During the track mode, SW1 is closed and the
VG VG
output V
V V V V
OUT follows the input signal VIN. In the hold mode,
S D S D
SW1 is opened and the signal is held by the hold capacitor CH. Due to switch and capacitor leakage, the voltage on the hold
T P-CHANNEL T N-CHANNEL T P+ P+ N+ N+ R R R
capacitor will decrease with time. The ADG511/ADG512/
E E E
ADG513 minimizes this droop due to its low leakage specifica-
N N N C C C
tions. The droop rate is further minimized by the use of a poly-
H H P– N– H
styrene hold capacitor. The droop rate for the circuit shown is
BURIED OXIDE LAYER
typically 15 µV/µs.
SUBSTRATE (BACKGATE)
A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both Figure 2. Trench Isolation switches will be at the same potential, they will have a differen- tial effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation –8– REV. C