ADG528FPIN CONFIGURATION AND FUNCTION DESCRIPTIONSA0WRNCRSA13212019EN4PIN 118 A2INDENTFIERV517SSGNDADG528FS1 616 VDDTOP VIEWS2 715(Not to Scale)S5S3 814 S6910111213S4D 7 NCS8S7 00 5- NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 65 09 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No.MnemonicDescription 1 NC No Connect. This pin is open. 2 WR Write. The WR signal latches the state of the address control lines and the enable line. 3 A0 Logic Control Input. 4 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 5 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 6 S1 Source Terminal 1. This pin can be an input or an output. 7 S2 Source Terminal 2. This pin can be an input or an output. 8 S3 Source Terminal 3. This pin can be an input or an output. 9 S4 Source Terminal 4. This pin can be an input or an output. 10 D Drain Terminal. This pin can be an input or an output. 11 NC No Connect. This pin is open. 12 S8 Source Terminal 8. This pin can be an input or an output. 13 S7 Source Terminal 7. This pin can be an input or an output. 14 S6 Source Terminal 6. This pin can be an input or an output. 15 S5 Source Terminal 5. This pin can be an input or an output. 16 VDD Most Positive Power Supply Potential. 17 GND Ground (0 V) Reference. 18 A2 Logic Control Input. 19 A1 Logic Control Input. 20 RS Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off ). Rev. F | Page 7 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY TRUTH TABLE TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE