Datasheet ADG726, ADG732 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 16-/32-Channel, 4 Ω, +1.8 V to +5.5 V and ±2.5 V Analog Multiplexers |
| Seiten / Seite | 21 / 8 — ADG726/ADG732. Data Sheet. ADG726/. ADG732. −40°C to. Parameter Symbol. … |
| Revision | C |
| Dateiformat / Größe | PDF / 350 Kb |
| Dokumentensprache | Englisch |
ADG726/ADG732. Data Sheet. ADG726/. ADG732. −40°C to. Parameter Symbol. +25°C. +85°C. +125°C. Unit Test. Conditions/Comments
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ADG726/ADG732 Data Sheet ADG726/ ADG732 ADG732 −40°C to −40°C to Parameter Symbol +25°C +85°C +125°C Unit Test Conditions/Comments
Off Switch Source Capacitance CS (Off) 13 pF typ Off Switch Drain Capacitance CD (Off) ADG726 137 pF typ f = 1 MHz ADG732 275 pF typ f = 1 MHz On Switch Drain, Source CD, CS (On) Capacitance ADG726 150 pF typ f = 1 MHz ADG732 300 pF typ f = 1 MHz POWER REQUIREMENTS Positive Supply Current IDD 10 μA typ VDD = 2.75 V 20 20 μA max Digital inputs = 0 V or 2.75 V Negative Supply Current ISS 10 μA typ VDD = −2.75 V 20 20 μA max Digital inputs = 0 V or 2.75 V 1 Guaranteed by design; not subject to production test.
TIMING CHARACTERISTICS Table 4. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Test Conditions/Comments
t1 0 ns min CS to WR setup time t2 0 ns min CS to WR hold time t3 10 ns min WR pulse width t4 10 ns min Time between WR cycles t5 5 ns min Address, enable setup time t6 2 ns min Address, enable hold time 1 See Figure 3. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD). 3 Guaranteed by design and characterization, not production tested.
CS t1 t2 t3 t4 WR t5 t6
3
A0, A1, A2, A3, (A4)
-00
EN
765 02 Figure 3. Timing Diagram Figure 3 shows the timing sequence for latching the switch Input data is latched on the rising edge of WR. The ADG726 address and enable inputs. The latches are level sensitive; therefore, has two CS inputs. This enables the device to be used either as a while WR is held low, the latches are transparent and the switches dual 16-to-1 channel multiplexer or a differential 16-channel respond to changing the address and enable the inputs. multiplexer. If a differential output is required, tie CSA and CSB together. Rev. C | Page 8 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS +5 V SINGLE SUPPLY +3 V SINGLE SUPPLY ±2.5 V DUAL SUPPLY TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP 48-LEAD LFCSP Truth Tables TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
ADG726/ADG732 Data Sheet ADG726/ ADG732 ADG732 −40°C to −40°C to Parameter Symbol +25°C +85°C +125°C Unit Test Conditions/Comments
Off Switch Source Capacitance CS (Off) 13 pF typ Off Switch Drain Capacitance CD (Off) ADG726 137 pF typ f = 1 MHz ADG732 275 pF typ f = 1 MHz On Switch Drain, Source CD, CS (On) Capacitance ADG726 150 pF typ f = 1 MHz ADG732 300 pF typ f = 1 MHz POWER REQUIREMENTS Positive Supply Current IDD 10 μA typ VDD = 2.75 V 20 20 μA max Digital inputs = 0 V or 2.75 V Negative Supply Current ISS 10 μA typ VDD = −2.75 V 20 20 μA max Digital inputs = 0 V or 2.75 V 1 Guaranteed by design; not subject to production test.
TIMING CHARACTERISTICS Table 4. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Test Conditions/Comments
t1 0 ns min CS to WR setup time t2 0 ns min CS to WR hold time t3 10 ns min WR pulse width t4 10 ns min Time between WR cycles t5 5 ns min Address, enable setup time t6 2 ns min Address, enable hold time 1 See Figure 3. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD). 3 Guaranteed by design and characterization, not production tested.
CS t1 t2 t3 t4 WR t5 t6
3
A0, A1, A2, A3, (A4)
-00
EN
765 02 Figure 3. Timing Diagram Figure 3 shows the timing sequence for latching the switch Input data is latched on the rising edge of WR. The ADG726 address and enable inputs. The latches are level sensitive; therefore, has two CS inputs. This enables the device to be used either as a while WR is held low, the latches are transparent and the switches dual 16-to-1 channel multiplexer or a differential 16-channel respond to changing the address and enable the inputs. multiplexer. If a differential output is required, tie CSA and CSB together. Rev. C | Page 8 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS +5 V SINGLE SUPPLY +3 V SINGLE SUPPLY ±2.5 V DUAL SUPPLY TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP 48-LEAD LFCSP Truth Tables TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE