Datasheet ADG633 (Analog Devices) - 5

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Data Sheet ADG633
VDD = 2.7 V to 3.6 V, VSS = 0 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 3. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 to VDD V VDD = 2.7 V, VSS = 0 V On Resistance, RON 185 Ω typ VS = 0 V to 2.7 V, IS = 0.1 mA; see Figure 20 300 350 400 Ω max VS = 0 V to 2.7 V, IS = 0.1 mA; see Figure 20 On-Resistance Match 2 Ω typ VS = +1.5 V, IS = 0.1 mA Between Channels, ΔRON 4.5 6 7 Ω max VS = +1.5 V, IS = 0.1 mA LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS(OFF) ±0.005 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21 ±0.2 ±5 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21 Drain Off Leakage, ID(OFF) ±0.005 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22 ±0.2 ±5 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22 Channel On Leakage, ID(ON), IS(ON) ±0.005 nA typ VS = VD = 1 V or 3 V; see Figure 23 ±0.2 ±5 nA max VS = VD = 1 V or 3 V; see Figure 23 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.5 V max Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH ±1 μA max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pF typ DYNAMIC CHARACTERISTICS1 tTRANSITION 170 ns typ RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24 300 370 400 ns max RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24 tON (EN) 200 ns typ RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 310 380 420 ns max RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 tOFF (EN) 30 ns typ RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 40 55 75 ns max RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 Break-Before-Make Time Delay, tBBM 180 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25 Charge Injection 1 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 2 pC max VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 −3 dB Bandwidth 500 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS(OFF) 5 pF typ f = 1 MHz CD(OFF) 8 pF typ f = 1 MHz CD(ON), CS(ON) 12 pF typ f = 1 MHz POWER REQUIREMENTS2 VDD = 3.3 V IDD 0.01 μA typ Digital inputs = 0 V or 3.3 V 1 μA max Digital inputs = 0 V or 3.3 V 1 Guaranteed by design; not subject to production test. 2 The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance, leakage, VINL, VINH, and switching times. The optimal power-up sequence for the device is: ground, VDD, VSS, and then the digital inputs, before applying the analog input signal. Rev. B | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY OPERATION SINGLE-SUPPLY OPERATION ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES