Datasheet ADG1206, ADG1207 (Analog Devices) - 10

HerstellerAnalog Devices
BeschreibungLow Capacitance, 16-and 8-Channel, ±15 V/+12 V iCMOS Multiplexers
Seiten / Seite20 / 10 — ADG1206/ADG1207. Data Sheet. CI B. CI A CI. 28 DA. DB 2. 27 VSS. NIC 3. …
RevisionC
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DokumentenspracheEnglisch

ADG1206/ADG1207. Data Sheet. CI B. CI A CI. 28 DA. DB 2. 27 VSS. NIC 3. 26 S8A. S8B 1. 24 S8A. S7B 2. 23 S7A. S8B 4. 25 S7A. S6B 3. 22 S6A. S7B 5. 24 S6A

ADG1206/ADG1207 Data Sheet CI B CI A CI 28 DA DB 2 27 VSS NIC 3 26 S8A S8B 1 24 S8A S7B 2 23 S7A S8B 4 25 S7A S6B 3 22 S6A S7B 5 24 S6A

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ADG1206/ADG1207 Data Sheet CI B D CI S D CI A CI S N D N V N D N V V 1 DD 28 DA 32 31 30 29 28 27 26 25 DB 2 27 VSS NIC 3 26 S8A S8B 1 24 S8A S7B 2 23 S7A S8B 4 25 S7A S6B 3 22 S6A S7B 5 24 S6A S5B 4 ADG1207 21 S5A S4B 5 TOP VIEW 20 S4A S6B 6 23 S5A (Not to Scale) ADG1207 S3B 6 19 S3A S5B 7 22 S4A S2B 7 18 S2A TOP VIEW S1B 8 17 S1A S4B 8 (Not to Scale) 21 S3A S3B 9 20 S2A 9 10 11 12 13 14 15 16 S2B 10 19 S1A D 2 C C C 1 0 N N A I I I N N N A A E S1B G 11 18 EN 1. NIC = NO INTERNAL CONNECTION. GND 12 17 A0 2. THE EXPOSED PAD MUST BE TIED
-037
NIC 13 16 A1 TO THE SUBSTRATE, V
119
SS.
06
NIC 14 15 A2
6 03 9-
NIC = NO INTERNAL CONNECTION
611 0 Figure 5. 28-Lead TSSOP Pin Configuration (ADG1207) Figure 6. 32-Lead LFCSP Pin Configuration (ADG1207)
Table 6. ADG1207 Pi n Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description
1 29 VDD Most Positive Power Supply Potential. 2 31 DB Drain Terminal B. Can be an input or an output. 3, 13, 14 11, 12, 13, 26, NIC No Internal Connection. 28, 30, 32 4 1 S8B Source Terminal 8B. Can be an input or an output. 5 2 S7B Source Terminal 7B. Can be an input or an output. 6 3 S6B Source Terminal 6B. Can be an input or an output. 7 4 S5B Source Terminal 5B. Can be an input or an output. 8 5 S4B Source Terminal 4B. Can be an input or an output. 9 6 S3B Source Terminal 3B. Can be an input or an output. 10 7 S2B Source Terminal 2B. Can be an input or an output. 11 8 S1B Source Terminal 1B. Can be an input or an output. 12 9 GND Ground (0 V) Reference. 15 10 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. 18 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1A Source Terminal 1A. Can be an input or an output. 20 18 S2A Source Terminal 2A. Can be an input or an output. 21 19 S3A Source Terminal 3A. Can be an input or an output. 22 20 S4A Source Terminal 4A. Can be an input or an output. 23 21 S5A Source Terminal 5A. Can be an input or an output. 24 22 S6A Source Terminal 6A. Can be an input or an output. 25 23 S7A Source Terminal 7A. Can be an input or an output. 26 24 S8A Source Terminal 8A. Can be an input or an output. 27 25 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 27 DA Drain Terminal A. Can be an input or an output. Not 0 EPAD Exposed Pad. The exposed pad must be tied to the substrate, VSS. applicable Rev. C | Page 10 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE