Datasheet ADG1414 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 9.5 Ω RON ±15 V/+12 V/±5 V iCMOS Serially-Controlled Octal SPST Switches |
| Seiten / Seite | 19 / 8 — ADG1414. Data Sheet. TIMING CHARACTERISTICS. Table 6. Parameter Limit. … |
| Revision | B |
| Dateiformat / Größe | PDF / 536 Kb |
| Dokumentensprache | Englisch |
ADG1414. Data Sheet. TIMING CHARACTERISTICS. Table 6. Parameter Limit. TMIN, TMAX Unit. Conditions/Comments. Timing Diagrams. t10. SCLK
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ADG1414 Data Sheet TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit at TMIN, TMAX Unit Conditions/Comments
t 1 1 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 5 ns min SYNC to SCLK active edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 5 ns min SCLK active edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 5 ns min SYNC rising edge to next SCLK active edge ignored t10 5 ns min SCLK active edge to SYNC falling edge ignored t 2 11 40 ns max SCLK rising edge to SDO valid t12 15 ns min Minimum RESET pulse width 1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 2 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams t10 t1 t9 SCLK t t8 t 2 3 t7 t4 SYNC t6 t5 DIN DB7 DB0 RESET
02 0
t
7-
12
49 08 Figure 2. Serial Write Operation
t1 SCLK 8 16 t t t 2 9 t 3 8 t4 t7 SYNC t5 t6 DIN DB7 DB0 DB7 DB0 INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N + 1 t11 SDO DB31 DB0
3 -00 97
UNDEFINED INPUT WORD FOR DEVICE N
84 0 Figure 3. Daisy-Chain Timing Diagram Rev. B | Page 8 of 19 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply ±5 V Dual Supply Continuous Current per Channel Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Serial Interface Input Shift Register Power-On Reset Daisy Chaining Outline Dimensions Ordering Guide
ADG1414 Data Sheet TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit at TMIN, TMAX Unit Conditions/Comments
t 1 1 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 5 ns min SYNC to SCLK active edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 5 ns min SCLK active edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 5 ns min SYNC rising edge to next SCLK active edge ignored t10 5 ns min SCLK active edge to SYNC falling edge ignored t 2 11 40 ns max SCLK rising edge to SDO valid t12 15 ns min Minimum RESET pulse width 1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 2 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams t10 t1 t9 SCLK t t8 t 2 3 t7 t4 SYNC t6 t5 DIN DB7 DB0 RESET
02 0
t
7-
12
49 08 Figure 2. Serial Write Operation
t1 SCLK 8 16 t t t 2 9 t 3 8 t4 t7 SYNC t5 t6 DIN DB7 DB0 DB7 DB0 INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N + 1 t11 SDO DB31 DB0
3 -00 97
UNDEFINED INPUT WORD FOR DEVICE N
84 0 Figure 3. Daisy-Chain Timing Diagram Rev. B | Page 8 of 19 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply ±5 V Dual Supply Continuous Current per Channel Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Serial Interface Input Shift Register Power-On Reset Daisy Chaining Outline Dimensions Ordering Guide