Datasheet ADGS1412 (Analog Devices) - 3

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Data Sheet ADGS1412 SPECIFICATIONS ±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1. −40°C to −40°C to Parameter +25°C +85°C +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 1.5 Ω typ VS = ±10 V, IS = −10 mA, see Figure 29 1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V On-Resistance Match Between 0.1 Ω typ VS = ±10 V, IS = −10 mA Channels, ∆RON 0.18 0.19 0.21 Ω max On-Resistance Flatness, RFLAT (ON) 0.3 Ω typ VS = ±10 V, IS = −10 mA 0.36 0.4 0.45 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V Source Off Leakage, IS (Off ) ±0.03 nA typ VS = ±10 V, VD =  10 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off ) ±0.03 nA typ VS = ±10 V, VD =  10 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±10 V, see Figure 28 ±2 ±4 ±30 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA High Impedance Leakage Current 0.001 μA typ Output voltage (VOUT) = ground voltage (VGND) or VL ±0.1 μA max High Impedance Output Capacitance 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 tON 400 ns typ Load resistance (RL) = 300 Ω, load capacitance (CL) = 35 pF 475 480 485 ns max VS = 10 V, see Figure 37 tOFF 160 ns typ RL = 300 Ω, CL = 35 pF 190 210 225 ns max VS = 10 V, see Figure 37 Break-Before-Make Time Delay, tD 215 ns typ RL = 300 Ω, CL = 35 pF 170 ns min VS1 = VS2 = 10 V, see Figure 36 Charge Injection, QINJ −20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38 Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31 Channel to Channel Crosstalk −100 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30 Total Harmonic Distortion + Noise 0.014 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see Figure 33 Rev. B | Page 3 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE