Datasheet ADGS1208, ADGS1209 (Analog Devices) - 6

HerstellerAnalog Devices
BeschreibungSPI Interface, Low CON and QINJ, ±15 V/+12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches
Seiten / Seite33 / 6 — ADGS1208/. ADGS1209. Data Sheet. Parameter. +25°C. −40°C to +85°C −40°C …
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ADGS1208/. ADGS1209. Data Sheet. Parameter. +25°C. −40°C to +85°C −40°C to +125°C Unit. Test Conditions/Comments

ADGS1208/ ADGS1209 Data Sheet Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

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ADGS1208/ ADGS1209 Data Sheet Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 ±0.1 ±0.6 ±1.0 nA max Drain Off Leakage, ID (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 ±0.1 ±0.6 ±1.0 nA max Channel On Leakage, ID (On), IS (On) ±0.02 nA typ VS = VD = 1 V/10 V, see Figure 32 ±0.3 ±0.6 ±1.0 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA High Impedance Leakage Current 0.001 µA typ VOUT = VGND or VL ±0.1 µA max High Impedance Output Capacitance 4 pF typ GPOx Output Voltage High, VOH VL − 0.2 V V min ISOURCE = 100 µA Low, VOL 0.2 V max ISINK = 100 µA Timing tON 95 ns typ CL = 15 pF, see Figure 44 115 115 115 ns max tOFF 15 ns typ CL = 15 pF, see Figure 44 20 25 25 ns max Break-Before-Make Time Delay, tD 50 ns typ CL = 15 pF, see Figure 45 35 ns min DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTIC1 Transition Time, tTRANSITION 110 ns typ RL = 300 Ω, CL = 35 pF 185 220 245 ns max VS = 8 V, see Figure 41 tON (EN) 120 ns typ RL = 300 Ω, CL = 35 pF 140 190 210 ns max VS = 8 V, see Figure 42 tOFF (EN) 130 ns typ RL = 300 Ω, CL = 35 pF 145 195 215 ns max VS = 8 V, see Figure 42 Break-Before-Make Time Delay, tD 35 ns typ RL = 300 Ω, CL = 35 pF 15 ns min VS1 = VS2 = 8 V, see Figure 40 Charge Injection, QINJ pC typ V −0.2 S = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 43 Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 Channel to Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 Rev. 0 | Page 6 of 33 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Round Robin Mode General-Purpose Outputs Applications Information Digital Input Buffers Settling Time Power Supply Rails Power Supply Recommendations Register Summaries Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Round Robin Enable Register Round Robin Channel Configuration Register CNV Edge Select Register Software Reset Register Outline Dimensions Ordering Guide