Datasheet ADGS1414D (Analog Devices) - 4

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ADGS1414D Data Sheet Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
Break-Before-Make Time 215 ns typ RL = 300 Ω, CL = 35 pF Delay, tD 170 ns min Source 1 voltage, VS1 = Source 2 voltage, VS2 = 10 V, see Figure 36 Charge Injection, QINJ −20 pC typ VS = 0 V, source resistance, RS = 0 Ω, CL = 1 nF, see Figure 38 Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, frequency, f = 1 MHz, see Figure 31 Channel to Channel −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Crosstalk Figure 30 Total Harmonic Distortion + 0.014 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, Noise, THD + N see Figure 33 −3 dB Bandwidth 170 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 34 Insertion Loss −0.2 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 Source Capacitance, CS (Off) 20 pF typ VS = 0 V, f = 1 MHz Drain Capacitance, CD (Off) 21 pF typ VS = 0 V, f = 1 MHz CD (On), CS (On) 111 pF typ VS = 0 V, f = 1 MHz POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V Positive Supply Current, IDD 0.04 µA typ All switches open 4.0 µA max 480 µA typ All switches closed, VL = 5.5 V 800 µA max 480 µA typ All switches closed, VL = 2.7 V 800 µA max Load Current, IL Inactive 6.3 µA typ Digital inputs = 0 V or VL 8.0 µA max Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 7 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL, VL = 5 V 210 µA typ CS = VL and SDI = 0 V or VL, VL = 3 V Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V 7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V 120 µA typ CS and SCLK = 0 V or VL, VL = 3 V Active at 50 MHz 1.8 mA typ Digital inputs toggle between 0 V and VL, VL = 5.5 V 2.1 mA max 0.7 mA typ Digital inputs toggle between 0 V and VL, VL = 2.7 V 1.0 mA max Negative Supply Current, ISS 0.04 µA typ Digital inputs = 0 V or VL 4.0 µA max VDD/VSS ±4.5/±16.5 V min/V max GND = 0 V 1 Guaranteed by design. Not subject to production test. Rev. 0 | Page 4 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide