Datasheet AEM00940 (E-peas) - 9

link to page 15 link to page 14 link to page 14 link to page 15 link to page 15 link to page 14
DATASHEET AEM00940 5. Recommended Operation Conditions
Symbol Parameter Min Typ Max Unit CSRC Capacitor decoupling the BUFSRC pin. 8 10 µF CBOOST Capacitor of the boost converter. 10 22 25 µF LBOOST Inductor of the boost converter. 4 10 25 µF CBUCK Capacitor of the buck converter 8 10 22 µF LBUCK Inductor of the buck converter 4 10 25 µF CLV Capacitor decoupling the low-voltage LDO regulator. 8 10 14 µF CHV Capacitor decoupling the high-voltage LDO regulator. 8 10 14 µF CBATT
Optional
- Capacitor on BATT if no storage element is connected (see Section 8.4). 150 µF
Optional
- Resistor for setting threshold voltage of the battery RT in custom mode. 1 10 100 MΩ Equal to R1 + R2 + R3 + R4 (see Section 8.1.1).
Optional
- Resistor for setting the output voltage of the high- RV voltage LDO in custom mode. 1 10 40 MΩ Equal to R5 + R6 (see Section 8.1.1). RP
Optional
- Resistor to be used with a primary battery. Equal to R7 + R8 (see Section 8.3). 100 500 kΩ RS Resistor to be used for the source voltage regulation Equal to R9 + R10 (see Section 8.2). 0.1 1 MΩ Logic high (VOH) 1.75 V ENHV Enabling pin for the high-voltage LDO1. BUCK VBUCK V Logic low (VOL) -0.01 0 0.01 Logic high (VOH) 1.75 V ENLV Enabling pin for the low-voltage LDO2. BUCK VBOOST V Logic low (VOL) -0.01 0 0.01 Logic high (VOH) Connect to BUCK CFG[2:0] Configuration pins for the storage element (see Table 9). Logic low (VOL) Connect to GND Logic high (VOH) Connect to BUCK SRC_LVL_RANGE[1:0] Configuration pins for the range of the source voltage regulation configuration Logic low (VOL) Connect to GND Table 7: Recommended operating conditions 1. ENHV can be dynamical y driven by a logic signal from the LV domain. For a static usage, connect to BUCK (High) or GND (Low). 2. ENLV can be dynamical y driven by a logic signal from the HV domain. For a static usage, connect to BUCK or BOOST (High) or GND (Low). DS_AEM00940_Rev1.0 Copyright © 2022 e-peas SA 9 Document Outline 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. Deep sleep & Wake up modes 7.1.1. Supercapacitor as a storage element. 7.1.2. Battery as a storage element. 7.2. Normal mode 7.2.1. Boost 7.2.2. Buck 7.2.3. LDO outputs 7.3. Overcharge mode 7.4. Primary mode 7.5. Shutdown mode 7.6. Balun for dual-cell supercapacitor 8. System configuration 8.1. Battery and LDOs configuration 8.1.1. Custom mode 8.2. Source voltage configuration 8.3. Primary battery configuration 8.4. No-battery configuration 8.5. Storage element information 8.6. External inductors information 8.7. External capacitors information 9. Typical Application Circuits 9.1. Example circuit 1 9.2. Example circuit 2 10. Performance Data 10.1. BOOST conversion efficiency for LBOOST = 10 µH 10.2. BOOST conversion efficiency for LBOOST = 22 µH 10.3. Quiescent current 10.4. High-voltage LDO regulation 10.5. Low-voltage LDO regulation 10.6. High-voltage LDO efficiency 10.7. Low-voltage LDO efficiency 11. Schematic 12. Layout Package Information 13.1. Plastic Quad Flatpack No-lead (QFN 28-pin 5x5mm) 13.2. Board Layout 14. Revision History