Datasheet AEM00330 (E-peas) - 5

DATASHEET AEM00330
AEM00330 Storage element • Li-ion cell Source SRC STO • LiFePO4 cell 140mV - 4.5V • Nimh cell MAX • Dual-cell supercapacitor • Single-cell supercapacitor • Other... LOAD 1.2V/1.8V/2.5V/3.3V 60mA Your circuit Figure 1: Simplified Schematic View
1. Introduction
The AEM00330 is a ful -featured energy efficient power VCHRDY, and reset when VSTO drops below VCHRDY. management circuit able to harvest energy from an energy ST_STO_OVDIS is asserted when VSTO drops below VOVDIS and source (connected to SRC) to supply an application circuit reset when VSTO is above VOVDIS. Status pin ST_LOAD is (connected to LOAD) and use any excess of energy to charge asserted when the load voltage VLOAD rises above VLOAD,TYP, a storage element (connected to STO). This is done with a and is reset when VLOAD drops below VLOAD,MIN. minimal bil of material: only 3 capacitors and one inductor Depending on the harvester and the application, the source are needed for a basic setup. regulation voltage, VSRC,REG, can be configured thanks to six The heart of the AEM00330 is a regulated switching DCDC configuration pins (SRC_LVL_CFG[5:0]). converter with high power conversion efficiency. Once started, if at any time the load requires more power At first start-up, as soon as a required cold-start voltage of than can be harvested from the energy source, the AEM00330 275 mV and a sparse amount of power of at least 3 μW is automatical y uses the storage element to keep the load available at the source, the AEM00330 coldstarts. After the supplied. cold start, the AEM extracts the power available from the The AEM00330’s DCDC converter can work in two modes: source if the working input voltage is higher than VSRC,REG. LOW POWER MODE and HIGH POWER MODE, each one of Through four configuration pins (STO_CFG[3:0]), the user can these being optimized for a power range on SRC and LOAD. select a specific operating mode out of 15 modes that cover The charging of the storage element can be prevented by most application requirements without any dedicated pul ing EN_STO_CH to GND, typical y to protect the storage external component. Those operating modes define the element if the temperature is too low/high to safely charge it. protection levels of the storage element. If none of those 15 modes fit the user’s storage element, a custom mode is also The AEM00330 also implements a SLEEP STATE, which available to al ow the user to define a mode with custom reduces the quiescent current to avoid wasting the energy specifications. stored on the storage element when EN_SLEEP is asserted. Status pins ST_STO, ST_STO_RDY and ST_STO_OVDIS provide At start-up, user can choose to prioritize starting the information about the voltage levels of the storage element. application circuit connected on LOAD, or charging the ST_STO is asserted when the voltage of the storage element storage element connected on STO. This is set by the VSTO is above VCHRDY and is reset when the voltage drops STO_PRIO pin. below VOVDIS. ST_STO_RDY is asserted when VSTO is above DS_AEM00330_Rev1.0 Copyright © 2022 e-peas SA 5 Document Outline Table of Contents List of Tables 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Source Voltage Regulation 7.7. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. Source Level Configuration 8.7. External Components 8.7.1. Storage element information 8.7.2. External inductor information 8.7.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.4. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 9.5. DCDC Conversion Efficiency From SRC to STO in High Power Mode 9.6. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 9.7. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10. Schematic 11. Layout 12. Package Information 12.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 12.2. Board Layout 13. Revision History