Datasheet SG1524, SG2524, SG3524 (Microchip) - 5

Application Notes (Continued)
CURRENT LIMITING
A second factor to consider is that the response time is The current limiting circuitry of the SG1524 is shown in Figure 4. relatively slow. The current limit amplifier is internally By matching the base-emitter voltages of Q1 and Q2, and compensated by R , C , and Q1, resulting in a roll-off pole at 1 1 assuming a negligible voltage drop across R1: approximately 300 Hz. A third factor to consider is the bias current of the C.L. sense pins. A constant current of C.L. Threshold = V (Q1) + I • R - V (Q2) = I • R approximately 150µA flows out of Pin 4, and a variable current BE 1 2 BE 1 2 ~ 200 mV with a range of 0-150µA flows out of Pin 5. As a result, the equivalent source impedance seen by the current sense pins Although this circuit provides a relatively small threshold with a should be less than 50 ohms to keep the threshold error less negligible temperature coefficient, there are some limitations to than 5%. its use because of its simplicity. Since the gain of this circuit is relatively low (42 dB), there is a The most important of these is the limited common-mode voltage transition region as the current limit amplifier takes over pulse range: ±0.3 volts around ground. This requires sensing in the width control from the error amplifier. For testing purposes, ground or return line of the power supply. Also precautions threshold is defined as the input voltage required to get 25% duty should be taken to not turn on the parasitic substrate diode of the cycle (+2 volts at the error amplifier output) with the error amplifier integrated circuit, even under transient conditions. A Schottky signaling maximum duty cycle. clamp diode at Pin 5 may be required in some configurations to APPLICATION NOTE: If the current limit function is not used on achieve this. the SG1524, the common-mode voltage range restriction re- quires both current sense pins to be grounded.
Figure 4 · Current Limiting Circuitry of the SG1524 1k 1k 5k 5k 5k 5k 5k 5k 5k 1k 5k 2k 1k 2k 3k 20k 50k
In this conventional single-ended regulator circuit, the two out- Push-pull outputs are used in this transformer-coupled DC-DC puts of the SG1524 are connected in parallel for effective 0 - 90% regulating converter. Note that the oscillator must be set at twice duty-cycle modulation. The use of an output inductor requires the desired output frequency as the SG1524's internal flip-flop and R-C phase compensation network for loop stability. divides the frequency by 2 as it switches the PWM signal from one output to the other. Current limiting is done here in the primary so that the pulse width will be reduced should transformer saturation occur. 5 Document Outline Regulating Pulse Width Modulator Description Features High Reliability Features Block Diagram Absolute Maximum Ratings Thermal Data Recommended Operating Conditions Electrical Characteristics Electrical Characteristics (Continued) Application Notes Application Notes (Continued) Connection Diagrams and Ordering Information Package Outline Dimensions Package Outline Dimensions (continued)