Datasheet MC14093B (ON Semiconductor) - 2

link to page 2 link to page 3 MC14093B Quad 2-Input “NAND" Schmitt Trigger The MC14093B Schmitt trigger is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14093B
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may be used in place of the MC14011B quad 2−input NAND gate for enhanced noise immunity or to “square up” slowly changing waveforms.
Features SOIC−14 SOEIAJ−14 TSSOP−14
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
D SUFFIX F SUFFIX DT SUFFIX
•
CASE 751A CASE 965 CASE 948G
Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature
PIN ASSIGNMENT
Range • Triple Diode Protection on All Inputs IN 1 1 14 V A DD • Pin−for−Pin Compatible with CD4093 IN 2 2 13 IN 2 A D • Can be Used to Replace MC14011B OUT 3 12 IN 1 A D • Independent Schmitt−Trigger at each Input OUT 4 11 OUT B D • NLV Prefix for Automotive and Other Applications Requiring IN 1 5 10 OUT B C Unique Site and Control Change Requirements; AEC−Q100 IN 2 6 9 IN 2 B C Qualified and PPAP Capable • V 7 8 IN 1C These Devices are Pb−Free and are RoHS Compliant SS
MAXIMUM RATINGS
(Voltages Referenced to VSS)
MARKING DIAGRAMS Symbol Parameter Value Unit
14 14 VDD DC Supply Voltage Range − 0.5 to +18.0 V 14093BG MC14093B Vin, Vout Input or Output Voltage Range − 0.5 to VDD + 0.5 V AWLYWW ALYWG (DC or Transient) 1 I 1 in, Iout Input or Output Current ±10 mA (DC or Transient) per Pin
SOIC−14 SOEIAJ−14
PD Power Dissipation, 500 mW 14 per Package (Note 1) 14 093B TA Ambient Temperature Range − 55 to +125 °C ALYW G T G stg Storage Temperature Range − 65 to +150 °C T 1 L Lead Temperature 260 °C (8−Second Soldering)
TSSOP−14
Stresses exceeding those listed in the Maximum Ratings table may damage the A = Assembly Location device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. WL, L = Wafer Lot 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C YY, Y = Year WW, W = Work Week This device contains protection circuitry to guard against damage due to high G or G = Pb−Free Package static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this (Note: Microdot may be in either location) high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
ORDERING INFORMATION
Unused inputs must always be tied to an appropriate logic voltage level See detailed ordering and shipping information in the package (e.g., either VSS or VDD). Unused outputs must be left open. dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 10 MC14093B/D