Datasheet FDV301N (Fairchild)
| Hersteller | Fairchild |
| Beschreibung | Digital FET, N-Channel |
| Seiten / Seite | 5 / 1 — June 2009. FDV301N Digital FET , N-Channel. General Description Features. … |
| Dateiformat / Größe | PDF / 243 Kb |
| Dokumentensprache | Englisch |
June 2009. FDV301N Digital FET , N-Channel. General Description Features. SOT-23. SuperSOTTM-6. SuperSOTTM-8. SO-8. SOT-223. SOIC-16
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June 2009 FDV301N Digital FET , N-Channel General Description Features
25 V, 0.22 A continuous, 0.5 A Peak. This N-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell R = 5 Ω @ V = 2.7 V DS(ON) GS density, DMOS technology. This very high density process is R = 4 Ω @ V = 4.5 V. DS(ON) GS especially tailored to minimize on-state resistance. This Very low level gate drive requirements allowing direct device has been designed especially for low voltage operation in 3V circuits. V < 1.06V. applications as a replacement for digital transistors. Since GS(th) bias resistors are not required, this one N-channel FET can Gate-Source Zener for ESD ruggedness. replace several different digital transistors, with different bias >6kV Human Body Model resistor values. Replace multiple NPN digital transistors with one DMOS FET.
SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 Mark:301 I N V E R T E R A P P L I C A T I O N
Vcc D D OUT IN G S G S GND
Absolute Maximum Ratings
T = 25oC unless other wise noted A
Symbol Parameter FDV301N Units
V , V Drain-Source Voltage, Power Supply Voltage 25 V DSS CC V , V Gate-Source Voltage, V 8 V GSS I IN I , I Drain/Output Current - Continuous 0.22 A D O 0.5 P Maximum Power Dissipation 0.35 W D T ,T Operating and Storage Temperature Range -55 to 150 °C J STG ESD Electrostatic Discharge Rating MIL-STD-883D 6.0 kV Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
Rθ Thermal Resistance, Junction-to-Ambient 357 °C/W JA ©2009 Fairchild Semiconductor Corporation FDV301N Rev.F1
25 V, 0.22 A continuous, 0.5 A Peak. This N-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell R = 5 Ω @ V = 2.7 V DS(ON) GS density, DMOS technology. This very high density process is R = 4 Ω @ V = 4.5 V. DS(ON) GS especially tailored to minimize on-state resistance. This Very low level gate drive requirements allowing direct device has been designed especially for low voltage operation in 3V circuits. V < 1.06V. applications as a replacement for digital transistors. Since GS(th) bias resistors are not required, this one N-channel FET can Gate-Source Zener for ESD ruggedness. replace several different digital transistors, with different bias >6kV Human Body Model resistor values. Replace multiple NPN digital transistors with one DMOS FET.
SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 Mark:301 I N V E R T E R A P P L I C A T I O N
Vcc D D OUT IN G S G S GND
Absolute Maximum Ratings
T = 25oC unless other wise noted A
Symbol Parameter FDV301N Units
V , V Drain-Source Voltage, Power Supply Voltage 25 V DSS CC V , V Gate-Source Voltage, V 8 V GSS I IN I , I Drain/Output Current - Continuous 0.22 A D O 0.5 P Maximum Power Dissipation 0.35 W D T ,T Operating and Storage Temperature Range -55 to 150 °C J STG ESD Electrostatic Discharge Rating MIL-STD-883D 6.0 kV Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
Rθ Thermal Resistance, Junction-to-Ambient 357 °C/W JA ©2009 Fairchild Semiconductor Corporation FDV301N Rev.F1