Datasheet ADSP-TS101S (Analog Devices) - 4

ADSP-TS101S
The ADSP-TS101S, in most cases, has a two-cycle arithmetic • Register file—each compute block has a multiported execution pipeline that is fully interlocked, so whenever a com- 32-word, fully orthogonal register file used for transferring putation result is unavailable for another operation dependent data between the computation units and data buses and for on it, the DSP automatically inserts one or more stall cycles as storing intermediate results. Instructions can access the needed. Efficient programming with dependency-free instruc- registers in the register file individually (word aligned), or tions can eliminate most computational and memory transfer in sets of two (dual aligned) or four (quad aligned). data dependencies. • ALU—the ALU performs a standard set of arithmetic oper- ations in both fixed- and floating-point formats. It also performs logic operations.
ADSP-TS101S BOOT EPROM
• Multiplier—the multiplier performs both fixed- and float-
(OPTIONAL) LCLK_P BMS CS
ing-point multiplication and fixed-point multiply and
CLOCK SCLK_P ADDR
accumulate.
S/LCLK_N REFERENCE V DATA REF
• Shifter—the 64-bit shifter performs logical and arithmetic
BRST MEMORY LCLKRAT2–0 (OPTIONAL)
shifts, bit and bit stream manipulation, and field deposit
SCLKFREQ ADDR31–0 ADDR
and extraction operations.
IRQ3–0 SDRAM DATA63–0 DATA MEMORY FLAG3–0 RD OE
• Accelerator—128-bit unit for trellis decoding (for example,
(OPTIONAL) ID2–0 WRH/WRL WE
Viterbi and turbo decoders) and complex correlations for
CLK CS MSSD ACK ACK ADDR RAS
communication applications.
RAS MS1–0 CS DATA CAS CAS
Using these features, the compute blocks can:
LDQM DQM HOST MSH HDQM PROCESSOR
• Provide 8 MACs per cycle peak and 7.1 MACs per cycle
HBR WE INTERFACE SDWE (OPTIONAL) HBG
sustained 16-bit performance and provide 2 MACs per
CKE SDCKE
cycle peak and 1.8 MACs per cycle sustained 32-bit perfor-
A10 SDA10 ADDR BR7–0
mance (based on FIR)
FLYBY DATA CPA IOEN
• Execute six single-precision, floating-point or execute 24
DPA LXDAT7–0 LINK BOFF
fixed-point (16-bit) operations per cycle, providing
DMA DEVICE DEVICES LXCLKIN DMAR3–0 (OPTIONAL)
1,800 MFLOPS or 7.3 GOPS performance
(4 MAX) LXCLKOUT DATA (OPTIONAL) LXDIR
• Perform two complex 16-bit MACs per cycle
TMR0E
• Execute eight trellis butterflies in one cycle
BM L S BUSLOCK A O S T DATA ALIGNMENT BUFFER (DAB) R E A CONTROLIMP2–0 T R D N D DS2–0 O D
The DAB is a quad word FIFO that enables loading of quad
RESET JTAG C A
word data from nonaligned addresses. Normally, load instruc- tions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB signifi- Figure 2. Single-Processor System with External SDRAM cantly improves the efficiency of some applications, such as FIR filters. In addition, the ADSP-TS101S supports SIMD operations two
DUAL INTEGER ALUS (IALUS)
ways—SIMD compute blocks and SIMD computations. The programmer can direct both compute blocks to operate on the The ADSP-TS101S has two IALUs that provide powerful same data (broadcast distribution) or on different data (merged address generation capabilities and perform many general-pur- distribution). In addition, each compute block can execute four pose integer operations. Each of the IALUs: 16-bit or eight 8-bit SIMD computations in parallel. • Provides memory addresses for data and update pointers
DUAL COMPUTE BLOCKS
• Supports circular buffering and bit-reverse addressing The ADSP-TS101S has compute blocks that can execute com- • Performs general-purpose integer operations, increasing putations either independently or together as a SIMD engine. programming flexibility The DSP can issue up to two compute instructions per compute • Includes a 31-word register file for each IALU block each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations. As address generators, the IALUs perform immediate or indi- rect (pre- and post-modify) addressing. They perform modulus The compute blocks are referred to as X and Y in assembly syn- and bit-reverse operations with no constraints placed on mem- tax, and each block contains three computational units—an ory addresses for the modulus data buffer placement. Each ALU, a multiplier, a 64-bit shifter, and a 32-word register file. IALU can specify either a single, dual, or quad word access from memory. Rev. D | Page 4 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide