Datasheet PMG1-S2 (Infineon) - 3

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PMG1-S2 Datasheet
Table 1 shows the comparison of features of different MCUs of the PMG1 family.
Table 1. Comparison of Features of Different PMG1 Family MCUs Subsystem or Range Item PMG1-S0 PMG1-S1 PMG1-S2 PMG1-S3*
CPU & Memory Core Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0+ Subsystem Max Freq (MHz) 48 48 48 48 Flash (KB) 64 128 128 256 SRAM (KB) 8 12 8 32 Power Delivery Power Delivery Ports 1 1 1 1 port for 48-QFN 2 ports for 97-BGA Role Sink DRP DRP DRP MOSFET Gate Drivers 1x PFET 2x PFET 2x NFET Flexible 2x NFET Fault Protections VBUS OVP and UVP VBUS OVP, UVP, and OCP VBUS OVP, UVP, and VBUS OVP, UVP, and OCP SCP and RCP (for Source OCP SCP and RCP (for Source Configuration only) Configuration only) USB Integrated Full Speed No No Yes Yes USB 2.0 Device with Billboard Class support Voltage Range Supply (V) VDDD (2.7 - 5.5) VSYS (2.75 - 5.5) VSYS (2.7 - 5.5) VSYS (2.8–5.5) VBUS (4 - 21.5) VBUS (4 - 21.5) VBUS (4 - 21.5) VBUS (4–28) IO (V) 1.71 - 5.5 1.71 - 5.5 1.71 - 5.5 1.71 – 5.5 Digital SCB (configurable as 2 4 4 7 for 48-QFN (out of which I2C/UART/SPI) only 5 can be configured as SPI and UART) 8 for 97-BGA TCPWM Block (configurable 4 2 4 7 for 48-QFN as timer, counter or pulse 8 for 97-BGA width modulator) Hardware Authentication No No Yes (AES-128/192/256, Yes (AES-128, SHA2-256, Block (Crypto) SHA1, SHA2-224, TRNG, Vector Unit) SHA2-256, PRNG, CRC) Analog ADC 2x 8-bit SAR 1x 8-bit SAR 2x 8-bit SAR 2x 8-bit SAR 1x 12-bit SAR On-chip Temperature Sensor Yes Yes Yes Yes Direct Memory DMA No No No Yes Access (DMA) GPIO Max # of I/O 12(10+2 OVT) 17(15+2 OVT) 20(18+2 OVT) 26 (24+2 OVT) for 48-QFN 50 (48+2 OVT) for 97-BGA Charging Charging Source - BC 1.2, AC BC 1.2, AC BC 1.2, AC, AFC and Quick Standards Charge 3.0 Charging Sink BC 1.2, Apple BC 1.2, AC BC 1.2, AC BC 1.2, AC Charging (AC) ESD Protection ESD Protection Yes (Up to ± 8-kV Yes (Human Body model Yes (Up to ± 8-kV Yes (Human Body model contact discharge, up and Charged Device contact discharge, up to and Charged Device Model) to ±15-kV air Model) ±15-kV air discharge, discharge, Human Human body model and body model, and charged device model) charged device model) Packages Package Options 24-QFN (4x4 mm, 40-QFN (6×6 mm, 0.5-mm 40-QFN (6×6 mm, 48-QFN (6x6 mm, 0.5-mm 0.5-mm pitch) pitch) 0.5-mm pitch) pitch) 97-BGA (6x6 mm, 0.5 mm and 0.65 mm pitch) * Contact the local Cypress sales office to get more information about PMG1-S2. The rest of this document discusses the PMG1-S2 device in detail. Document Number: 002-31598 Rev. *B Page 2 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support