Datasheet STL200N45LF7 (STMicroelectronics) - 4
| Hersteller | STMicroelectronics |
| Beschreibung | N-channel 45 V, 1.4 mOhm typ., 120 A STripFET F7 Power MOSFET in a PowerFLAT 5x6 package |
| Seiten / Seite | 14 / 4 — Electrical characteristics. STL200N45LF7. Table 4: On/off-state. Symbol. … |
| Dateiformat / Größe | PDF / 910 Kb |
| Dokumentensprache | Englisch |
Electrical characteristics. STL200N45LF7. Table 4: On/off-state. Symbol. Parameter. Test conditions. Min. Typ. Max. Unit. Table 5: Dynamic
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Electrical characteristics STL200N45LF7 2 Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 45 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 45 V 1 µA IGSS Gate body leakage current VDS = 0, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1.2 V VGS = 10 V, ID = 18 A 1.4 1.8 mΩ RDS(on) Static drain-source on-resistance VGS = 4.5 V, ID = 18 A 2 2.5 mΩ
Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 5170 - pF VDS = 25 V, f = 1 MHz, Coss Output capacitance - 1190 - pF VGS = 0 V Crss Reverse transfer capacitance - 68 - pF Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A 0.5 0.9 2 Ω Qg Total gate charge VDD = 22.5 V, ID = 36 A - 33 - nC VGS= 4.5 V, Qgs Gate-source charge - 15 - nC see Figure 14: "Test circuit for gate charge Qgd Gate-drain charge - 10 - nC behavior"
Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD= 22.5 V, ID = 18 A, - 25 - ns RG = 4.7 Ω tr Rise time - 6 - ns VGS = 10 V (see Figure td(off) Turn-off delay time 13: "Test circuit for - 58 - ns resistive load switching times" and Figure 18: tf Fall time - 7 - ns "Switching time waveform") 4/14 DocID027980 Rev 4
Electrical characteristics STL200N45LF7 2 Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 45 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 45 V 1 µA IGSS Gate body leakage current VDS = 0, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1.2 V VGS = 10 V, ID = 18 A 1.4 1.8 mΩ RDS(on) Static drain-source on-resistance VGS = 4.5 V, ID = 18 A 2 2.5 mΩ
Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 5170 - pF VDS = 25 V, f = 1 MHz, Coss Output capacitance - 1190 - pF VGS = 0 V Crss Reverse transfer capacitance - 68 - pF Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A 0.5 0.9 2 Ω Qg Total gate charge VDD = 22.5 V, ID = 36 A - 33 - nC VGS= 4.5 V, Qgs Gate-source charge - 15 - nC see Figure 14: "Test circuit for gate charge Qgd Gate-drain charge - 10 - nC behavior"
Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD= 22.5 V, ID = 18 A, - 25 - ns RG = 4.7 Ω tr Rise time - 6 - ns VGS = 10 V (see Figure td(off) Turn-off delay time 13: "Test circuit for - 58 - ns resistive load switching times" and Figure 18: tf Fall time - 7 - ns "Switching time waveform") 4/14 DocID027980 Rev 4