Datasheet PIC16F688 (Microchip) - 5

PIC16F688 Pin Diagram (QFN) 16-pin QFN
DD SS V NC NC V 16 15 14 13 RA5/T1CKI/OSC1/CLKIN 1 12 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 2 11 RA1/AN1/C1IN-/VREF/ICSPCLK
PIC16F688
RA3/MCLR/VPP 3 10 RA2/AN2/T0CKI/INT/C1OUT RC5/RX/DT 4 9 RC0/AN4/C2IN+ 5 6 7 8 /CK IN- X /AN7 /AN6 /C2 RC3 RC2 OUT/T /AN5 /C2 4 RC1 RC
TABLE 2: PIC16F688 16-PIN SUMMARY (QFN) I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic
RA0 12 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT RA1 11 AN1 C1IN- — — IOC Y VREF/ICSPCLK RA2 10 AN2 C1OUT T0CKI — IOC/INT Y — RA3 3 — — — — IOC Y
(1)
MCLR/VPP RA4 2 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 1 — — T1CKI — IOC Y OSC1/CLKIN RC0 9 AN4 C2IN+ — — — — — RC1 8 AN5 C2IN- — — — — — RC2 7 AN6 — — — — — — RC3 6 AN7 — — — — — — RC4 5 — C2OUT — TX/CK — — — RC5 4 — — — RX/DT — — — — 16 — — — — — — VDD — 13 — — — — — — VSS — 14 — — — — — — NC — 15 — — — — — — NC
Note 1:
Pull-up activated only with external MCLR configuration. © 2009 Microchip Technology Inc. DS41203E-page 3 Document Outline High-Performance RISC CPU: Special Microcontroller Features: Low-Power Features: Peripheral Features: Pin Diagram (PDIP, SOIC, TSSOP) TABLE 1: PIC16F688 14-Pin Summary (PDIP, SOIC, TSSOP) Pin Diagram (QFN) TABLE 2: PIC16F688 16-Pin Summary (QFN) Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC16F688 Block Diagram TABLE 1-1: PIC16F688 Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: Program Memory Map And Stack For The PIC16F688 2.2 Data Memory Organization 2.2.1 General Purpose Register File 2.2.2 Special FUNCTION Registers FIGURE 2-2: PIC16F688 Special Function Registers TABLE 2-1: PIC16F688 Special Registers Summary Bank 0 TABLE 2-2: PIC16F688 Special Function Registers Summary Bank 1 TABLE 2-3: PIC16F688 Special Registers Summary Bank 2 TABLE 2-4: PIC16F688 Special Function Registers Summary Bank 3 Register 2-1: STATUS: STATUS Register Register 2-2: OPTION_REG: Option Register Register 2-3: INTCON: Interrupt Control Register Register 2-4: PIE1: Peripheral Interrupt Enable Register 1 Register 2-5: PIR1: Peripheral Interrupt Request Register 1 Register 2-6: PCON: Power Control Register 2.3 PCL and PCLATH FIGURE 2-3: Loading Of PC In Different Situations 2.3.1 computed goto 2.3.2 Stack 2.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing FIGURE 2-4: Direct/indirect Addressing PIC16F688 3.0 Oscillator Module (With Fail-Safe Clock Monitor) 3.1 Overview FIGURE 3-1: PIC® MCU Clock Source Block Diagram 3.2 Oscillator Control Register 3-1: OSCCON: Oscillator Control Register 3.3 Clock Source Modes 3.4 External Clock Modes 3.4.1 Oscillator Start-up Timer (OST) TABLE 3-1: Oscillator Delay Examples 3.4.2 EC Mode FIGURE 3-2: External Clock (EC) Mode Operation 3.4.3 LP, XT, HS Modes FIGURE 3-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 3-4: Ceramic Resonator Operation (XT or HS Mode) 3.4.4 External RC Modes FIGURE 3-5: External RC Modes 3.5 Internal Clock Modes 3.5.1 INTOSC and INTOSCIO Modes 3.5.2 HFINTOSC Register 3-2: OSCTUNE: Oscillator Tuning ReGister 3.5.3 LFINTOSC 3.5.4 Frequency Select Bits (IRCF) 3.5.5 HF and LF INTOSC Clock Switch Timing FIGURE 3-6: Internal Oscillator Switch Timing 3.6 Clock Switching 3.6.1 System Clock Select (SCS) Bit 3.6.2 Oscillator Start-up Time-out Status (OSTS) Bit 3.7 Two-Speed Clock Start-up Mode 3.7.1 Two-Speed Start-up Mode Configuration 3.7.2 Two-Speed Start-up Sequence 3.7.3 Checking Two-Speed Clock Status FIGURE 3-7: Two-Speed Start-up 3.8 Fail-Safe Clock Monitor FIGURE 3-8: FSCM Block Diagram 3.8.1 Fail-Safe Detection 3.8.2 Fail-Safe Operation 3.8.3 Fail-Safe Condition Clearing 3.8.4 Reset or Wake-up from Sleep FIGURE 3-9: FSCM Timing Diagram TABLE 3-2: Summary of Registers Associated with Clock Sources 4.0 I/O Ports 4.1 PORTA and the TRISA Registers EXAMPLE 4-1: INITIALIZING PORTA Register 4-1: PORTA: PORTA Register Register 4-2: TRISA: PORTA Tri-State Register 4.2 Additional Pin Functions 4.2.1 ANSEL Register 4.2.2 Weak Pull-ups 4.2.3 INTERRUPT-ON-CHANGE Register 4-3: ANSEL: Analog Select Register Register 4-4: WPUA: Weak Pull-Up PORTA Register Register 4-5: IOCA: Interrupt-on-change PORTA Register 4.2.4 Ultra Low-Power Wake-up EXAMPLE 4-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION 4.2.5 Pin Descriptions and Diagrams FIGURE 4-1: Block Diagram of RA0 FIGURE 4-2: Block Diagram Of RA1 FIGURE 4-3: Block Diagram Of RA2 FIGURE 4-4: Block Diagram Of RA3 FIGURE 4-5: Block Diagram Of RA4 FIGURE 4-6: Block Diagram Of RA5 TABLE 4-1: Summary of Registers Associated with PORTA 4.3 PORTC EXAMPLE 4-3: INITIALIZING PORTC Register 4-6: PORTC: PORTC Register Register 4-7: TRISC: PORTC Tri-State Register 4.3.1 RC0/AN4/C2IN+ 4.3.2 RC1/AN5/C2IN- FIGURE 4-7: Block Diagram Of RC0 And RC1 4.3.3 RC2/AN6 4.3.4 RC3/AN7 FIGURE 4-8: Block Diagram Of RC2 And RC3 4.3.5 RC4/C2OUT/TX/CK FIGURE 4-9: Block Diagram Of RC4 4.3.6 RC5/RX/DT FIGURE 4-10: Block Diagram Of RC5 Pin TABLE 4-2: Summary of Registers Associated with PORTC 5.0 Timer0 Module 5.1 Timer0 Operation 5.1.1 8-bit Timer mode 5.1.2 8-Bit Counter Mode FIGURE 5-1: Block Diagram of the Timer0/WDT Prescaler 5.1.3 Software Programmable Prescaler EXAMPLE 5-1: Changing Prescaler (Timer0 ® WDT) EXAMPLE 5-2: Changing Prescaler (WDT ® TIMER0) 5.1.4 Timer0 Interrupt 5.1.5 Using Timer0 with an External Clock Register 5-1: OPTION_REG: Option Register TABLE 5-1: Summary of Registers Associated with Timer0 6.0 Timer1 Module with Gate Control 6.1 Timer1 Operation 6.2 Clock Source Selection FIGURE 6-1: Timer1 Block Diagram 6.2.1 iNternal Clock Source 6.2.2 External Clock Source 6.3 Timer1 Prescaler 6.4 Timer1 Oscillator 6.5 Timer1 Operation in Asynchronous Counter Mode 6.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode 6.6 Timer1 Gate 6.7 Timer1 Interrupt 6.8 Timer1 Operation During Sleep FIGURE 6-2: Timer1 Incrementing Edge 6.9 Timer1 Control Register Register 6-1: T1CON: Timer 1 Control Register TABLE 6-1: Summary of Registers Associated with Timer1 7.0 Comparator Module 7.1 Comparator Overview FIGURE 7-1: Single Comparator FIGURE 7-2: Comparator C1 Output Block Diagram FIGURE 7-3: Comparator C2 Output Block Diagram 7.1.1 Analog Input Connection Considerations FIGURE 7-4: Analog Input Model 7.2 Comparator Configuration FIGURE 7-5: Comparator I/O Operating Modes 7.3 Comparator Control 7.3.1 Comparator Output State 7.3.2 Comparator Output Polarity TABLE 7-1: Output state vs. input conditions 7.3.3 Comparator Input Switch 7.4 Comparator Response Time 7.5 Comparator Interrupt Operation FIGURE 7-6: Comparator Interrupt Timing W/O CMCON0 Read FIGURE 7-7: Comparator Interrupt Timing With CMCON0 Read 7.6 Operation During Sleep 7.7 Effects of a Reset Register 7-1: CMCON0: Comparator Configuration Register 7.8 Comparator C2 Gating Timer1 7.9 Synchronizing Comparator C2 Output to Timer1 Register 7-2: CMCON1: Comparator Configuration Register 7.10 Comparator Voltage Reference 7.10.1 Independent Operation 7.10.2 Output Voltage Selection EQUATION 7-1: CVref Output Voltage 7.10.3 Output Clamped to Vss 7.10.4 Output Ratiometric to Vdd Register 7-3: VRCON: Voltage Reference Control register FIGURE 7-8: Comparator Voltage Reference Block Diagram TABLE 7-2: Summary of Registers Associated with the Comparator and Voltage Reference Modules 8.0 Analog-to-Digital Converter (ADC) Module FIGURE 8-1: ADC Block Diagram 8.1 ADC Configuration 8.1.1 Port Configuration 8.1.2 Channel Selection 8.1.3 ADC Voltage Reference 8.1.4 Conversion Clock TABLE 8-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies (Vdd > 3.0V) FIGURE 8-2: Analog-to-Digital Conversion Tad Cycles 8.1.5 Interrupts 8.1.6 Result Formatting FIGURE 8-3: 10-Bit A/D Conversion Result Format 8.2 ADC Operation 8.2.1 Starting a Conversion 8.2.2 Completion of a Conversion 8.2.3 Terminating a conversion 8.2.4 ADC Operation During Sleep 8.2.5 A/D Conversion Procedure EXAMPLE 8-1: A/D Conversion 8.2.6 ADC Register Definitions Register 8-1: ADCON0: A/D Control Register 0 Register 8-2: ADCON1: A/D Control Register 1 Register 8-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 8-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 8-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 8-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 8.3 A/D Acquisition Requirements EQUATION 8-1: Acquisition Time Example FIGURE 8-4: Analog Input Model FIGURE 8-5: ADC Transfer Function TABLE 8-2: Summary of Associated ADC Registers 9.0 Data EEPROM and Flash Program Memory Control 9.1 EEADR and EEADRH Registers 9.1.1 EECON1 and EECON2 Registers Register 9-1: EEDAT: EEPROM Data Register Register 9-2: EEADR: EEPROM Address Register Register 9-3: EEDATH: EEPROM Data hIGH bYTE Register Register 9-4: EEADRH: EEPROM Address hIGH bYTE Register Register 9-5: EECON1: EEPROM Control Register 9.1.2 Reading the Data EEPROM Memory EXAMPLE 9-1: Data EEPROM Read 9.1.3 Writing to the Data EEPROM Memory EXAMPLE 9-2: Data EEPROM Write 9.1.4 Reading the Flash Program Memory EXAMPLE 9-3: Flash Program Read FIGURE 9-1: Flash Program Memory Read Cycle Execution TABLE 9-1: Summary of Registers Associated with Data EEPROM 10.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 10-1: EUSART Transmit Block Diagram FIGURE 10-2: EUSART Receive Block Diagram 10.1 EUSART Asynchronous Mode 10.1.1 EUSART Asynchronous Transmitter FIGURE 10-3: Asynchronous Transmission FIGURE 10-4: Asynchronous Transmission (Back-to-Back) TABLE 10-1: Registers Associated with Asynchronous Transmission 10.1.2 EUSART Asynchronous Receiver FIGURE 10-5: Asynchronous Reception TABLE 10-2: Registers Associated with Asynchronous Reception 10.2 Clock Accuracy with Asynchronous Operation Register 10-1: TXSTA: Transmit STATUS AND CONTROL REGISTER Register 10-2: RCSTA: Receive STATUS AND CONTROL REGISTER(1) Register 10-3: BAUDCTL: BAUD RATE CONTROL REGISTER 10.3 EUSART Baud Rate Generator (BRG) EXAMPLE 10-1: Calculating Baud Rate Error TABLE 10-3: Baud Rate Formulas TABLE 10-4: Registers Associated with the bAUD rATE gENERATOR TABLE 10-5: BAUD Rates for Asynchronous Modes 10.3.1 Auto-Baud Detect TABLE 10-6: BRG Counter Clock Rates FIGURE 10-6: Automatic Baud Rate Calculation 10.3.2 AUTO-BAUD OVERFLOW 10.3.3 Auto-Wake-up on Break FIGURE 10-7: Auto-Wake-up bit (WUE) timing during normal operation FIGURE 10-8: Auto-Wake-up bit (WUE) timings during Sleep 10.3.4 BREAK Character Sequence 10.3.5 Receiving a BREAK Character FIGURE 10-9: Send Break Character Sequence 10.4 EUSART Synchronous Mode 10.4.1 Synchronous Master Mode FIGURE 10-10: Synchronous Transmission FIGURE 10-11: Synchronous Transmission (Through TXEN) TABLE 10-7: Registers Associated with Synchronous Master Transmission FIGURE 10-12: Synchronous Reception (Master Mode, SREN) TABLE 10-8: Registers Associated with Synchronous Master Reception 10.4.2 Synchronous slave Mode TABLE 10-9: Registers Associated with Synchronous Slave Transmission TABLE 10-10: Registers Associated with Synchronous Slave Reception 11.0 Special Features of the CPU 11.1 Configuration Bits Register 11-1: CONFIG: Configuration Word Register 11.2 Reset FIGURE 11-1: Simplified Block Diagram Of On-Chip Reset Circuit 11.2.1 Power-On Reset 11.2.2 MCLR FIGURE 11-2: Recommended MCLR Circuit 11.2.3 Power-up Timer (PWRT) 11.2.4 Brown-Out Reset (BOR) FIGURE 11-3: Brown-Out Situations 11.2.5 Time-out Sequence 11.2.6 Power Control (PCON) Register TABLE 11-1: Time-Out In Various Situations TABLE 11-2: PCON Bits And Their Significance TABLE 11-3: Summary of Registers Associated with Brown-out Reset FIGURE 11-4: Time-Out Sequence On Power-Up (Delayed MCLR) FIGURE 11-5: Time-Out Sequence On Power-Up (Delayed MCLR) FIGURE 11-6: Time-Out Sequence On Power-Up (MCLR With Vdd) TABLE 11-4: Initialization Condition For Registers TABLE 11-4: Initialization Condition For Registers (Continued) TABLE 11-5: Initialization Condition For Special Registers 11.3 Interrupts 11.3.1 RA2/INT Interrupt 11.3.2 Timer0 Interrupt 11.3.3 PORTA Interrupt FIGURE 11-7: Interrupt Logic FIGURE 11-8: INT Pin Interrupt Timing TABLE 11-6: Summary of Registers Associated with Interrupts 11.4 Context Saving During Interrupts EXAMPLE 11-1: Saving Status and W Registers in RAM 11.5 Watchdog Timer (WDT) 11.5.1 WDT Oscillator 11.5.2 WDT Control FIGURE 11-9: Watchdog Timer Block Diagram TABLE 11-7: WDT Status Register 11-2: WDTCON: Watchdog Timer Control Register TABLE 11-8: Summary of Registers Associated with Watchdog Timer 11.6 Power-Down Mode (Sleep) 11.6.1 Wake-up from Sleep 11.6.2 Wake-up Using Interrupts FIGURE 11-10: Wake-Up From Sleep Through Interrupt 11.7 Code Protection 11.8 ID Locations 11.9 In-Circuit Serial Programming FIGURE 11-11: Typical In-Circuit Serial Programming Connection 11.10 In-Circuit Debugger TABLE 11-9: Debugger Resources FIGURE 11-12: 20-pin ICD Pinout 12.0 Instruction Set Summary 12.1 Read-Modify-Write Operations TABLE 12-1: Opcode Field Descriptions FIGURE 12-1: General Format for Instructions TABLE 12-2: PIC16F684 Instruction Set 12.2 Instruction Descriptions 13.0 Development Support 13.1 MPLAB Integrated Development Environment Software 13.2 MPASM Assembler 13.3 MPLAB C18 and MPLAB C30 C Compilers 13.4 MPLINK Object Linker/ MPLIB Object Librarian 13.5 MPLAB ASM30 Assembler, Linker and Librarian 13.6 MPLAB SIM Software Simulator 13.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 13.8 MPLAB REAL ICE In-Circuit Emulator System 13.9 MPLAB ICD 2 In-Circuit Debugger 13.10 MPLAB PM3 Device Programmer 13.11 PICSTART Plus Development Programmer 13.12 PICkit 2 Development Programmer 13.13 Demonstration, Development and Evaluation Boards 14.0 Electrical Specifications Absolute Maximum Ratings(†) FIGURE 14-1: PIC16F688 Voltage-Frequency Graph, -40°C £ ta £ +125°C FIGURE 14-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature 14.1 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) 14.2 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) 14.3 DC Characteristics: PIC16F688-I (Industrial) 14.4 DC Characteristics: PIC16F688-E (Extended) 14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) 14.6 Thermal Considerations 14.7 Timing Parameter Symbology FIGURE 14-3: Load Conditions 14.8 AC Characteristics: PIC16F688 (Industrial, Extended) FIGURE 14-4: Clock Timing TABLE 14-1: Clock Oscillator Timing Requirements TABLE 14-2: Oscillator Parameters FIGURE 14-5: CLKOUT and I/O Timing TABLE 14-3: CLKOUT and I/O Timing Parameters FIGURE 14-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 14-7: Brown-out Reset Timing and Characteristics TABLE 14-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Parameters FIGURE 14-8: Timer0 and Timer1 External Clock Timings TABLE 14-5: Timer0 and Timer1 External Clock Requirements TABLE 14-6: Comparator Specifications TABLE 14-7: Comparator Voltage Reference (CVref) Specifications TABLE 14-8: PIC16F688 A/D Converter (ADC) Characteristics TABLE 14-9: PIC16F688 A/D Conversion Requirements FIGURE 14-9: PIC16F688 A/D Conversion Timing (Normal Mode) FIGURE 14-10: PIC16F688 A/D Conversion Timing (Sleep Mode) 15.0 DC and AC Characteristics Graphs and Tables FIGURE 15-1: Typical Idd vs. Fosc Over Vdd (EC Mode) FIGURE 15-2: Maximum Idd vs. Fosc Over Vdd (EC Mode) FIGURE 15-3: Typical Idd vs. Fosc Over Vdd (HS Mode) FIGURE 15-4: Maximum Idd vs. Fosc Over Vdd (HS Mode) FIGURE 15-5: Typical Idd vs. Vdd Over Fosc (XT Mode) FIGURE 15-6: Maximum Idd vs. Vdd Over Fosc (XT Mode) FIGURE 15-7: Typical Idd vs. Vdd Over Fosc (EXTRC Mode) FIGURE 15-8: Maximum Idd vs. Vdd (EXTRC Mode) FIGURE 15-9: Idd vs. Vdd Over Fosc (LFINTOSC Mode, 31 kHz) FIGURE 15-10: Idd vs. Vdd (LP Mode) FIGURE 15-11: Typical Idd vs. Fosc Over Vdd (HFINTOSC Mode) FIGURE 15-12: Maximum Idd vs. Fosc Over Vdd (HFINTOSC Mode) FIGURE 15-13: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled) FIGURE 15-14: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled) FIGURE 15-15: Comparator Ipd vs. Vdd (Both Comparators Enabled) FIGURE 15-16: BOR Ipd VS. Vdd Over Temperature FIGURE 15-17: Typical WDT Ipd VS. Vdd (25°C) FIGURE 15-18: Maximum WDT Ipd VS. Vdd Over Temperature FIGURE 15-19: WDT Period VS. Vdd Over Temperature FIGURE 15-20: WDT Period VS. Temperature FIGURE 15-21: CVref Ipd VS. Vdd Over Temperature (High Range) FIGURE 15-22: CVref Ipd VS. Vdd Over Temperature (Low Range) FIGURE 15-23: Vol VS. Iol Over Temperature (Vdd = 3.0V) FIGURE 15-24: Vol VS. Iol Over Temperature (Vdd = 5.0V) FIGURE 15-25: Voh VS. Ioh Over Temperature (Vdd = 3.0V) FIGURE 15-26: Voh VS. Ioh Over Temperature (Vdd = 5.0V) FIGURE 15-27: TTL Input Threshold Vin VS. Vdd Over Temperature FIGURE 15-28: Schmitt Trigger Input Threshold Vin VS. Vdd Over Temperature FIGURE 15-29: T1OSC Ipd vs. Vdd Over Temperature (32 kHz) FIGURE 15-30: Comparator Response Time (Rising Edge) FIGURE 15-31: Comparator Response Time (Falling Edge) FIGURE 15-32: LFINTOSC Frequency vs. Vdd Over Temperature (31 kHz) FIGURE 15-33: ADC Clock Period vs. Vdd Over Temperature FIGURE 15-34: Typical HFINTOSC Start-Up Times vs. Vdd Over Temperature FIGURE 15-35: Maximum HFINTOSC Start-Up Times vs. Vdd Over Temperature FIGURE 15-36: Minimum HFINTOSC Start-Up Times vs. Vdd Over Temperature FIGURE 15-37: Typical HFINTOSC Frequency Change vs. Vdd (25°C) FIGURE 15-38: Typical HFINTOSC Frequency Change Over Device Vdd (85°C) FIGURE 15-39: Typical HFINTOSC Frequency Change vs. Vdd (125°C) FIGURE 15-40: Typical HFINTOSC Frequency Change vs. Vdd (-40°C) 16.0 Packaging Information 16.1 Package Marking Information 16.2 Package Details Appendix A: Data Sheet Revision History Revision A Revision B Revision C Revision D Revision E Appendix B: Migrating from other PIC® Devices TABLE B-1: Feature Comparison INDEX The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Product Identification System Worldwide Sales