Datasheet MAX4571, MAX4572, MAX4573, MAX4574 (Maxim) - 10

Serially Controlled, Clickless Audio/Video Switches Detailed Description
uration of the data bits and their related switches. The arrangement of the command bits and the data bits The MAX4571–MAX4574 are serial-interface controlled depends on the interface type (2-wire or 3-wire). After a switches with soft-mode “clickless” and hard-mode oper- SWITCHSET command is issued, a logic 1 in any data- ating capability. The MAX4571/MAX4573 contain 11 bit location closes the associated switch, while a logic 0 SPST switches, while the MAX4572/MAX4574 contain opens it. After a MODESET command, a logic 1 in any two SPST switches and six SPDT switches. The SPDT data-bit location sets the associated switch into hard switches are actually 2-to-1 multiplexers, in that each mode, while a logic 0 sets it into soft mode. SPDT is really two independent SPST switches with a common node, as shown in the Pin Configurations. Each
2-Wire Serial Interface
switch is controlled independently by either the SPI or The MAX4571/MAX4572 use a 2-wire, I2C-compatible I2C interface. serial interface requiring only two I/O lines of a stan- Audio off-isolation is -90dB at 20kHz, crosstalk is at dard microprocessor port for communication. These least -90dB at 20kHz, and video off-isolation is at least devices use the SendByte™ and WriteWord™ proto- -50dB at 10MHz. cols. The SendByte protocol is used only for the RESET command. The WriteWord protocol is used for the Each switch of any device may be set to operate in MODESET and SWITCHSET commands. either soft or hard mode. In soft mode, the switching transition is slowed to avoid the audible “clicking” that The first byte of any 2-wire serial-interface transaction is
MAX4571–MAX4574
can occur when switches are used to route audio sig- always the address byte. To address a given chip, the nals. In hard mode, the switches are not slowed down, A0 and A1 bits in the address byte (Table 3) must dupli- making this mode useful when a faster response is cate the values present at the A0 and A1 pins of that required. If a new command is issued while any soft- chip, and the rest of the address bits must be config- mode switch is transitioning, the switch transition time ured as shown in Table 3. Connect the A0 and A1 pins is decreased so it reaches its final state before the new to V+ or to GND, or drive them with CMOS logic levels. command is executed. Soft mode is the power-up The second byte is the command byte. The possible default state for all switches. Switches in the same commands are RESET, MODESET, and SWITCHSET. mode are guaranteed to be break-before-make relative RESET sets all switches to the initial power-up state to each other. Break-before-make does not apply (open and in soft switching mode). The RESET com- between switches operating in different modes. mand is executed on the rising clock edge of the These devices operate from a single supply of +2.7V to acknowledge bit after the command byte. The MODE- +5.25V. The MAX4571/MAX4572 feature a 2-wire, I2C- SET and SWITCHSET commands are each followed by compatible serial interface, and the MAX4573/ two data bytes. The first data byte is buffered so all the MAX4574 feature a 3-wire, SPI/QSPI/MICROWIRE-com- data latches switch together. MODESET and SWITCH- patible serial interface. SET are executed on the rising clock edge of the acknowledge bit after the second data byte. Table 3
Applications Information
details the 2-wire interface data structure. Figures 3 and 4 and the I/O Interface Characteristics detail the
Switch Control
timing of the 2-wire serial-interface protocol. All bytes of The MAX4571–MAX4574 have a common command the transmission, whether address, command, or data, and control-bit structure, the differences being only in are sent MSB first. the interface type (2-wire or 3-wire) and in the switch The MAX4571/MAX4572 are receive-only devices and configurations. must be controlled by a bus master device. A bus mas- The SWITCHSET command controls the open/closed ter signals the beginning of a transmission with a start states of the various switches. MODESET controls condition by transitioning SDA from high to low while soft/hard-mode states of the switches. There are also SCL is high. The slave devices monitor the serial bus NO_OP and RESET commands. The NO_OP command continuously, waiting for a start condition followed by an is useful for daisy-chaining multiple 3-wire parts. The address byte. When a device recognizes its address RESET command places a device in a state identical to byte, it acknowledges by pulling the SDA line low for its power-up state, with all switches open and in soft one clock period; it is then ready to accept command switching mode. and data bytes. The device then issues a similar Table 1 shows the configuration of the command bits acknowledgment after the command byte, and again and their related commands. Table 2 shows the config- after each data byte. When the master has finished SendByte and WriteWord are trademarks of Philips Corp.
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