Datasheet LNK3202, LNK3204-7, LNK3294, LNK3296 (Power Integrations) - 8
| Hersteller | Power Integrations |
| Beschreibung | Highly Energy Efficient Off-line Switcher IC with Integrated System Level Protection for Low Component-Count Power Supplies |
| Seiten / Seite | 28 / 8 — LinkSwitch-TN2. Topology. Basic Circuit Schematic. Key Features. BP/M. … |
| Dateiformat / Größe | PDF / 2.6 Mb |
| Dokumentensprache | Englisch |
LinkSwitch-TN2. Topology. Basic Circuit Schematic. Key Features. BP/M. LinkSwitch-TN2 Layout Considerations
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LinkSwitch-TN2 Topology Basic Circuit Schematic Key Features
1. Output referenced to input + 2. Positive output (V ) with respect to +V O IN 3. Step up/down – V > V or V < V O IN O IN Low-Side 4. Optocoupler feedback
LinkSwitch-TN2
Buck-Boost –
V V IN O
- Accuracy only limited by reference choice Optocoupler - Low cost non-safety rated optocoupler Feedback - No pre-load required
BP/M FB
+ 5. Fail-safe – output is not subjected to input
S D
voltage if the internal power MOSFET fails PI-7848-031616 6. Minimum no-load consumption Table 2 (cont). Common Circuit Configurations using LinkSwitch-TN2.
LinkSwitch-TN2 Layout Considerations
Figures 9a, 9b and 9c are printed circuit board layout design examples for the circuit schematic shown in Figure 8. The loop In the buck or buck-boost converter configuration, since the SOURCE formed between the LinkSwitch-TN2, inductor (L1), freewheeling pins in LinkSwitch-TN2 are switching nodes, the copper area diode (D1), and output capacitor (C2) should be kept as small as connected to SOURCE should be minimized to minimize EMI within possible. The BYPASS pin capacitor C1 should be located physical y the thermal constraints of the design. close to the SOURCE (S) and BYPASS (BP) pins. To minimize direct In the boost configuration, since the SOURCE pins are tied to DC coupling from switching nodes, the LinkSwitch-TN2 should be placed return, the copper area connected to SOURCE can be maximized to away from AC input lines. It may be advantageous to place capacitors improve heat sinking. C4 and C5 in-between LinkSwitch-TN2 and the AC input. The second rectifier diode D4 is optional, but may be included for better EMI performance and higher line surge withstand capability. Figure 9a. Recommended Printed Circuit Layout for LinkSwitch-TN2 using P Package.
8
Rev. M 10/20 www.power.com Document Outline Product Highlights Description Output Current Table Pin Functional Description LinkSwitch-TN2 Functional Description Applications Example Key Application Considerations Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Characteristics PDIP-8C (P Package) SMD-8C (G Package) SO-8C (D Package) PDIP-8C (P) and SMD-8C Package Marking SO-8C (D) Package Marking MSL Table ESD and Latch-Up Part Ordering Information
1. Output referenced to input + 2. Positive output (V ) with respect to +V O IN 3. Step up/down – V > V or V < V O IN O IN Low-Side 4. Optocoupler feedback
LinkSwitch-TN2
Buck-Boost –
V V IN O
- Accuracy only limited by reference choice Optocoupler - Low cost non-safety rated optocoupler Feedback - No pre-load required
BP/M FB
+ 5. Fail-safe – output is not subjected to input
S D
voltage if the internal power MOSFET fails PI-7848-031616 6. Minimum no-load consumption Table 2 (cont). Common Circuit Configurations using LinkSwitch-TN2.
LinkSwitch-TN2 Layout Considerations
Figures 9a, 9b and 9c are printed circuit board layout design examples for the circuit schematic shown in Figure 8. The loop In the buck or buck-boost converter configuration, since the SOURCE formed between the LinkSwitch-TN2, inductor (L1), freewheeling pins in LinkSwitch-TN2 are switching nodes, the copper area diode (D1), and output capacitor (C2) should be kept as small as connected to SOURCE should be minimized to minimize EMI within possible. The BYPASS pin capacitor C1 should be located physical y the thermal constraints of the design. close to the SOURCE (S) and BYPASS (BP) pins. To minimize direct In the boost configuration, since the SOURCE pins are tied to DC coupling from switching nodes, the LinkSwitch-TN2 should be placed return, the copper area connected to SOURCE can be maximized to away from AC input lines. It may be advantageous to place capacitors improve heat sinking. C4 and C5 in-between LinkSwitch-TN2 and the AC input. The second rectifier diode D4 is optional, but may be included for better EMI performance and higher line surge withstand capability. Figure 9a. Recommended Printed Circuit Layout for LinkSwitch-TN2 using P Package.
8
Rev. M 10/20 www.power.com Document Outline Product Highlights Description Output Current Table Pin Functional Description LinkSwitch-TN2 Functional Description Applications Example Key Application Considerations Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Characteristics PDIP-8C (P Package) SMD-8C (G Package) SO-8C (D Package) PDIP-8C (P) and SMD-8C Package Marking SO-8C (D) Package Marking MSL Table ESD and Latch-Up Part Ordering Information