Datasheet LM73100 (Texas Instruments) - 37

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LM7310 www.ti.com
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
Figure 8-12. LM73100 Reverse Current Protection Figure 8-13. LM73100 Reverse Current Protection During 20-V Hot-Plug at Output During 20-V Voltage Ramp at Output 8.6 Parallel Operation
Applications which need higher steady state current can use multiple LM73100 devices connected in parallel as shown in Figure 8-14 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The second device is held in an OFF state by driving its EN/UVLO pin low by the PG signal of the first device. Once the inrush sequence is complete, the first device asserts its PG pin high, allowing the second device to turn. The second device asserts its PG signal to indicate that it has turned on fully, thereby indicating to the system that the parallel combination is ready to deliver the full steady state current. Once in steady state, the devices share current nearly equally. There could be a slight skew in the currents depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM7310 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information