Datasheet TPS62902 (Texas Instruments) - 5
| Hersteller | Texas Instruments |
| Beschreibung | 3-V to 17-V, 2-A, high-efficiency and low IQ buck converter 1.5-mm × 2-mm QFN package |
| Seiten / Seite | 50 / 5 — TPS62902. www.ti.com. 6.4 Thermal Information. TPS6290x. THERMAL … |
| Dateiformat / Größe | PDF / 7.3 Mb |
| Dokumentensprache | Englisch |
TPS62902. www.ti.com. 6.4 Thermal Information. TPS6290x. THERMAL METRIC(1). VQFN 9-Pin. UNIT. JEDEC PCB. TPS6290xEVM-069
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TPS62902 www.ti.com
SLVSFM1 – MARCH 2021
6.4 Thermal Information TPS6290x THERMAL METRIC(1) VQFN 9-Pin UNIT JEDEC PCB TPS6290xEVM-069
RθJA Junction-to-ambient thermal resistance 97.2 73.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.4 N/A °C/W RθJB Junction-to-board thermal resistance 25 N/A °C/W ΨJT Junction-to-top characterization parameter 2.7 4.3 °C/W ΨJB Junction-to-board characterization parameter 24.7 28 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
VI = 3 V to 17 V, TJ = -40°C to +150°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY
Operating Quiescent Current (Power IQ_PSM Iout = 0 mA, device not switching 4 µA Save Mode) Operating Quiescent Current (PWM VIN=12 V, VOUT=1.2 V; Iout = 0 mA, IQ_PWM 8 mA Mode) device switching ISD Shutdown current into VIN pin EN = 0 V 0.27 3.5 µA Under Voltage Lock-Out VIN rising 2.85 2.925 3.0 V VUVLO Under Voltage Lock-Out VIN falling 2.7 2.775 2.85 V VUVLO_HYS Under Voltage Lock-Out Hysteresis Hysteresis 150 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN = 12 V 10 300 nA High-Level Input Voltage at MODE/S- VIH_MODE 1.0 V CONF-Pin Thermal Shutdown Threshold TJ rising 170 TSD °C Thermal Shutdown Hysteresis Hysteresis 20 VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V Smart-Enable Internal Pulldown REN_PD EN = LOW 0.5 MΩ Resistor VFB rising, referenced to VFB nominal 93.5% 96% 99% VPG Power good threshold VFB falling, referenced to VFB nominal 88.5% 93% 96% Hysteresis 1.5% 3.5% 6% VPG_OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V IPG_LKG Input leakage current into PG pin VPG = 5 V 15 550 nA tPG_DLY Power good delay time VFB falling 32 µs RSET S-CONF/VSET Resistor Tolerance -4 +4 % Maximum Capacitance connected to CSET 30 pF S-CONF/VSET Pins
POWER SWITCHES
ILKG_SW Leakage current into SW-Pin VSW = VOS = 5.5 V 2 7 µA High-side FET on resistance VIN > 4 V, ISW = 500 mA 62 111 RDS_ON mΩ Low-side FET on resistance VIN > 4 V, ISW = 500 mA 22 40 High-side FET current limit TPS62902 2.7 3.2 3.9 A ILIM Low-side FET current limit TPS62902 2.6 3 3.5 A Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS62902 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Mode Selection and Device Configuration MODE/S-CONF 7.3.2 Adjustable VO Operation (External Voltage Divider) 7.3.3 Setable VO Operation (VSET and Internal Voltage Divider) 7.3.4 Soft Start / Tracking (SS/TR) 7.3.5 Smart Enable with Precise Threshold 7.3.6 Power Good (PG) 7.3.7 Undervoltage Lockout (UVLO) 7.3.8 Current Limit And Short Circuit Protection 7.3.9 Thermal Shutdown 7.4 Device Functional Modes 7.4.1 Pulse Width Modulation (PWM) Operation 7.4.2 AEE (Automatic Efficiency Enhancement) 7.4.3 Power Save Mode Operation (Auto PFM/PWM) 7.4.4 100% Duty-Cycle Operation 7.4.5 Output Discharge Function 7.4.6 Starting into a Pre-Biased Load 8 Application and Implementation 8.1 Application Information 8.2 Typical Application with Adjustable Output Voltage 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH® Tools 8.2.2.2 Programming the Output Voltage 8.2.2.3 External Component Selection 8.2.2.4 Inductor Selection 8.2.2.5 Capacitor Selection 8.2.2.5.1 Output Capacitor 8.2.2.5.2 Input Capacitor 8.2.2.5.3 Soft-Start Capacitor 8.2.2.6 Tracking Function 8.2.2.7 Output Filter and Loop Stability 8.2.3 Application Curves 8.2.4 Typical Application with Setable VO using VSET 8.2.4.1 Design Requirements 8.2.4.2 Detailed Design Procedure 8.2.4.3 Application Curves 8.3 System Examples 8.3.1 LED Power Supply 8.3.2 Powering Multiple Loads 8.3.3 Voltage Tracking 8.3.4 Precise Soft-Start Timing 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 10.2.1 Thermal Considerations 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Custom Design With WEBENCH® Tools 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information
TPS62902 www.ti.com
SLVSFM1 – MARCH 2021
6.4 Thermal Information TPS6290x THERMAL METRIC(1) VQFN 9-Pin UNIT JEDEC PCB TPS6290xEVM-069
RθJA Junction-to-ambient thermal resistance 97.2 73.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.4 N/A °C/W RθJB Junction-to-board thermal resistance 25 N/A °C/W ΨJT Junction-to-top characterization parameter 2.7 4.3 °C/W ΨJB Junction-to-board characterization parameter 24.7 28 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
VI = 3 V to 17 V, TJ = -40°C to +150°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY
Operating Quiescent Current (Power IQ_PSM Iout = 0 mA, device not switching 4 µA Save Mode) Operating Quiescent Current (PWM VIN=12 V, VOUT=1.2 V; Iout = 0 mA, IQ_PWM 8 mA Mode) device switching ISD Shutdown current into VIN pin EN = 0 V 0.27 3.5 µA Under Voltage Lock-Out VIN rising 2.85 2.925 3.0 V VUVLO Under Voltage Lock-Out VIN falling 2.7 2.775 2.85 V VUVLO_HYS Under Voltage Lock-Out Hysteresis Hysteresis 150 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN = 12 V 10 300 nA High-Level Input Voltage at MODE/S- VIH_MODE 1.0 V CONF-Pin Thermal Shutdown Threshold TJ rising 170 TSD °C Thermal Shutdown Hysteresis Hysteresis 20 VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V Smart-Enable Internal Pulldown REN_PD EN = LOW 0.5 MΩ Resistor VFB rising, referenced to VFB nominal 93.5% 96% 99% VPG Power good threshold VFB falling, referenced to VFB nominal 88.5% 93% 96% Hysteresis 1.5% 3.5% 6% VPG_OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V IPG_LKG Input leakage current into PG pin VPG = 5 V 15 550 nA tPG_DLY Power good delay time VFB falling 32 µs RSET S-CONF/VSET Resistor Tolerance -4 +4 % Maximum Capacitance connected to CSET 30 pF S-CONF/VSET Pins
POWER SWITCHES
ILKG_SW Leakage current into SW-Pin VSW = VOS = 5.5 V 2 7 µA High-side FET on resistance VIN > 4 V, ISW = 500 mA 62 111 RDS_ON mΩ Low-side FET on resistance VIN > 4 V, ISW = 500 mA 22 40 High-side FET current limit TPS62902 2.7 3.2 3.9 A ILIM Low-side FET current limit TPS62902 2.6 3 3.5 A Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS62902 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Mode Selection and Device Configuration MODE/S-CONF 7.3.2 Adjustable VO Operation (External Voltage Divider) 7.3.3 Setable VO Operation (VSET and Internal Voltage Divider) 7.3.4 Soft Start / Tracking (SS/TR) 7.3.5 Smart Enable with Precise Threshold 7.3.6 Power Good (PG) 7.3.7 Undervoltage Lockout (UVLO) 7.3.8 Current Limit And Short Circuit Protection 7.3.9 Thermal Shutdown 7.4 Device Functional Modes 7.4.1 Pulse Width Modulation (PWM) Operation 7.4.2 AEE (Automatic Efficiency Enhancement) 7.4.3 Power Save Mode Operation (Auto PFM/PWM) 7.4.4 100% Duty-Cycle Operation 7.4.5 Output Discharge Function 7.4.6 Starting into a Pre-Biased Load 8 Application and Implementation 8.1 Application Information 8.2 Typical Application with Adjustable Output Voltage 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH® Tools 8.2.2.2 Programming the Output Voltage 8.2.2.3 External Component Selection 8.2.2.4 Inductor Selection 8.2.2.5 Capacitor Selection 8.2.2.5.1 Output Capacitor 8.2.2.5.2 Input Capacitor 8.2.2.5.3 Soft-Start Capacitor 8.2.2.6 Tracking Function 8.2.2.7 Output Filter and Loop Stability 8.2.3 Application Curves 8.2.4 Typical Application with Setable VO using VSET 8.2.4.1 Design Requirements 8.2.4.2 Detailed Design Procedure 8.2.4.3 Application Curves 8.3 System Examples 8.3.1 LED Power Supply 8.3.2 Powering Multiple Loads 8.3.3 Voltage Tracking 8.3.4 Precise Soft-Start Timing 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 10.2.1 Thermal Considerations 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Custom Design With WEBENCH® Tools 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information