Datasheet STM8S003F3, STM8S003K3 (STMicroelectronics) - 2

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Contents STM8S003F3 STM8S003K3 Contents 1 Introduction . 9 2 Description . 10 3 Block diagram . 11 4 Product overview . 12
4.1 Central processing unit STM8 . 12 4.2 Single wire interface module (SWIM) and debug module (DM) . 13 4.3 Interrupt controller . 13 4.4 Flash program memory and data EEPROM . 13 4.5 Clock controller . 15 4.6 Power management . 16 4.7 Watchdog timers . 16 4.8 Auto wakeup counter . 17 4.9 Beeper . 17 4.10 TIM1 - 16-bit advanced control timer . 17 4.11 TIM2 - 16-bit general purpose timer . 17 4.12 TIM4 - 8-bit basic timer . 18 4.13 Analog-to-digital converter (ADC1) . 18 4.14 Communication interfaces . 18 4.14.1 UART1 . 19 4.14.2 SPI . 19 4.14.3 I2C . 20
5 Pinouts and pin descriptions . 21
5.1 STM8S003K3 LQFP32 pinout and pin description . 22 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description . 25 5.3 Alternate function remapping . 29
6 Memory and register map . 30
6.1 Memory map . 30 6.2 Register map . 31 2/103 DS7147 Rev 10 Document Outline 1 Introduction 2 Description Table 1. STM8S003F3/K3 value line features 3 Block diagram Figure 1. STM8S003F3/K3 value line block diagram 4 Product overview 4.1 Central processing unit STM8 4.2 Single wire interface module (SWIM) and debug module (DM) 4.3 Interrupt controller 4.4 Flash program memory and data EEPROM Figure 2. Flash memory organization 4.5 Clock controller Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers 4.6 Power management 4.7 Watchdog timers 4.8 Auto wakeup counter 4.9 Beeper 4.10 TIM1 - 16-bit advanced control timer 4.11 TIM2 - 16-bit general purpose timer 4.12 TIM4 - 8-bit basic timer Table 3. TIM timer features 4.13 Analog-to-digital converter (ADC1) 4.14 Communication interfaces 4.14.1 UART1 4.14.2 SPI 4.14.3 I2C 5 Pinouts and pin descriptions Table 4. Legend/abbreviations for STM8S003F3/K3 pin description tables 5.1 STM8S003K3 LQFP32 pinout and pin description Figure 3. STM8S003K3 LQFP32 pinout Table 5. STM8S003K3 descriptions 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description Figure 4. STM8S003F3 TSSOP20 pinout Figure 5. STM8S003F3 UFQFPN20 pinout Table 6. STM8S003F3 pin description 5.3 Alternate function remapping 6 Memory and register map 6.1 Memory map Figure 6. Memory map Table 7. Flash, Data EEPROM and RAM boundary addresses 6.2 Register map 6.2.1 I/O port hardware register map Table 8. I/O port hardware register map 6.2.2 General hardware register map Table 9. General hardware register map 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 10. CPU/SWIM/debug module/interrupt controller registers 7 Interrupt vector mapping Table 11. Interrupt mapping 8 Option bytes Table 12. Option bytes Table 13. Option byte description 8.1 Alternate function remapping bits Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices 9 Electrical characteristics 9.1 Parameter conditions 9.1.1 Minimum and maximum values 9.1.2 Typical values 9.1.3 Typical curves 9.1.4 Loading capacitor Figure 7. Pin loading conditions 9.1.5 Pin input voltage Figure 8. Pin input voltage 9.2 Absolute maximum ratings Table 16. Voltage characteristics Table 17. Current characteristics Table 18. Thermal characteristics 9.3 Operating conditions Table 19. General operating conditions Figure 9. fCPUmax versus VDD Table 20. Operating conditions at power-up/power-down 9.3.1 VCAP external capacitor Figure 10. External capacitor CEXT 9.3.2 Supply current characteristics Table 21. Total current consumption with code execution in run mode at VDD = 5 V Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V Table 23. Total current consumption in wait mode at VDD = 5 V Table 24. Total current consumption in wait mode at VDD = 3.3 V Table 25. Total current consumption in active halt mode at VDD = 5 V Table 26. Total current consumption in active halt mode at VDD = 3.3 V Table 27. Total current consumption in halt mode at VDD = 5 V Table 28. Total current consumption in halt mode at VDD = 3.3 V Table 29. Wakeup times Table 30. Total current consumption and timing in forced reset state Table 31. Peripheral current consumption Figure 11. Typ. IDD(RUN) vs VDD, HSE user external clock, fCPU = 16 MHz Figure 12. Typ. IDD(RUN) vs fCPU, HSE user external clock, VDD = 5 V Figure 13. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz Figure 14. Typ. IDD(WFI) vs. VDD HSE user external clock, fCPU = 16MHz Figure 15. Typ. IDD(WFI) vs. fCPU, HSE user external clock, VDD = 5 V Figure 16. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz 9.3.3 External clock sources and timing characteristics Table 32. HSE user external clock characteristics Figure 17. HSE external clock source Table 33. HSE oscillator characteristics Figure 18. HSE oscillator circuit diagram 9.3.4 Internal clock sources and timing characteristics Table 34. HSI oscillator characteristics Figure 19. Typical HSI frequency variation vs VDD at 4 temperatures Table 35. LSI oscillator characteristics Figure 20. Typical LSI frequency variation vs VDD @ 4 temperatures 9.3.5 Memory characteristics Table 36. RAM and hardware registers Table 37. Flash program memory and data EEPROM 9.3.6 I/O port pin characteristics Table 38. I/O static characteristics Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures Figure 22. Typical pull-up resistance vs VDD @ 4 temperatures Figure 23. Typical pull-up current vs VDD @ 4 temperatures Table 39. Output driving current (standard ports) Table 40. Output driving current (true open drain ports) Table 41. Output driving current (high sink ports) Figure 24. Typ. VOL @ VDD = 5 V (standard ports) Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports) Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports) Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 9.3.7 Reset pin characteristics Table 42. NRST pin characteristics Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures Figure 37. Recommended reset pin protection 9.3.8 SPI serial peripheral interface Table 43. SPI characteristics Figure 38. SPI timing diagram - slave mode and CPHA = 0 Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) Figure 40. SPI timing diagram - master mode(1) 9.3.9 I2C interface characteristics Table 44. I2C characteristics Figure 41. Typical application with I2C bus and timing diagram 9.3.10 10-bit ADC characteristics Table 45. ADC characteristics Table 46. ADC accuracy with RAIN < 10 kW , VDD = 5 V Table 47. ADC accuracy with RAIN < 10 kW RAIN, VDD = 3.3 V Figure 42. ADC accuracy characteristics Figure 43. Typical application with ADC 9.3.11 EMC characteristics Table 48. EMS data Table 49. EMI data Table 50. ESD absolute maximum ratings Table 51. Electrical sensitivities 10 Package information 10.1 LQFP32 package information Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint Figure 46. LQFP32 marking example (package top view) 10.2 TSSOP20 package information Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint Figure 49. TSSOP20 marking example (package top view) 10.3 UFQFPN20 package information Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint Figure 52. UFQFPN20 marking example (package top view) 10.4 Thermal characteristics Table 55. Thermal characteristics 10.4.1 Reference document 10.4.2 Selecting the product temperature range 11 Ordering information Figure 53. STM8S003F3/K3 value line ordering information scheme(1) 12 STM8 development tools 12.1 Emulation and in-circuit debugging tools 12.2 Software tools 12.2.1 STM8 toolset 12.2.2 C and assembly toolchains 12.3 Programming tools 13 Revision history Table 56. Document revision history