Datasheet STK14C88C (Infineon)
| Hersteller | Infineon |
| Beschreibung | 256-Kbit (32K x 8) nvSRAM |
| Seiten / Seite | 21 / 1 — STK14C88C. 256-Kbit (32K × 8) nvSRAM. Features. Functional Description. … |
| Dateiformat / Größe | PDF / 458 Kb |
| Dokumentensprache | Englisch |
STK14C88C. 256-Kbit (32K × 8) nvSRAM. Features. Functional Description. Logic Block Diagram. Cypress Semiconductor Corporation
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STK14C88C
256-Kbit (32K × 8) nvSRAM
256-Kbit (32K × 8) nvSRAM Features Functional Description
■ 35 ns access time The Cypress STK14C88C is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 32KB. ■ Internally organized as 32K × 8 The embedded nonvolatile elements incorporate QuantumTrap ■ Hands-off automatic STORE on power-down with only a smal technology, producing the world’s most reliable nonvolatile capacitor memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable ■ STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or autostore on power-down QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place ■ RECALL to SRAM initiated by software or power-up automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. ■ Infinite read, write, and RECALL cycles Both the STORE and RECALL operations are also available ■ 1 million STORE cycles to QuantumTrap under software control. ■ 20-year data retention ■ Single 5 V + 10% operation ■ Industrial and Military temperatures ■ 32-pin CDIP package
Logic Block Diagram
VCC VCAP QuantumTrap 512 X 512 A POWER 5 CONTROL A6 STORE A7 A8 STATIC RAM RECALL STORE/ A9 ARRAY RECALL HSB A11 CONTROL 512 X 512 A12 A ROW DECODER 13 A14 SOFTWARE DETECT A13 - A0 COLUMN I/O DQ0 DQ1 COLUMN DEC DQ2 DQ BUFFERS 3 DQ4 DQ INPUT A A 5 0 A1 A A 2 3 4 A10 DQ6 DQ7 OE CE WE
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-23965 Rev. *A Revised March 26, 2019 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
256-Kbit (32K × 8) nvSRAM
256-Kbit (32K × 8) nvSRAM Features Functional Description
■ 35 ns access time The Cypress STK14C88C is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 32KB. ■ Internally organized as 32K × 8 The embedded nonvolatile elements incorporate QuantumTrap ■ Hands-off automatic STORE on power-down with only a smal technology, producing the world’s most reliable nonvolatile capacitor memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable ■ STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or autostore on power-down QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place ■ RECALL to SRAM initiated by software or power-up automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. ■ Infinite read, write, and RECALL cycles Both the STORE and RECALL operations are also available ■ 1 million STORE cycles to QuantumTrap under software control. ■ 20-year data retention ■ Single 5 V + 10% operation ■ Industrial and Military temperatures ■ 32-pin CDIP package
Logic Block Diagram
VCC VCAP QuantumTrap 512 X 512 A POWER 5 CONTROL A6 STORE A7 A8 STATIC RAM RECALL STORE/ A9 ARRAY RECALL HSB A11 CONTROL 512 X 512 A12 A ROW DECODER 13 A14 SOFTWARE DETECT A13 - A0 COLUMN I/O DQ0 DQ1 COLUMN DEC DQ2 DQ BUFFERS 3 DQ4 DQ INPUT A A 5 0 A1 A A 2 3 4 A10 DQ6 DQ7 OE CE WE
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-23965 Rev. *A Revised March 26, 2019 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support