Datasheet BD136G, BD138G, BD140G (ON Semiconductor) - 4
| Hersteller | ON Semiconductor |
| Beschreibung | 1.5 A POWER TRANSISTORS PNP SILICON 45, 60, 80 V, 12.5 W |
| Seiten / Seite | 5 / 4 — PACKAGE DIMENSIONS. TO−225. FRONT VIEW. BACK VIEW. SCALE 1:1. … |
| Revision | 16 |
| Dateiformat / Größe | PDF / 176 Kb |
| Dokumentensprache | Englisch |
PACKAGE DIMENSIONS. TO−225. FRONT VIEW. BACK VIEW. SCALE 1:1. MILLIMETERS. PIN 4. DIM. MIN. MAX. BACKSIDE TAB. GENERIC. MARKING DIAGRAM*. 2X b2
Modelllinie für dieses Datenblatt
Textversion des Dokuments
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS TO−225
CASE 77−09 4 ISSUE AD DATE 25 MAR 2015 1 2 3 3 2 1
FRONT VIEW BACK VIEW SCALE 1:1 E
NOTES: 1. DIMENSIONING AND TOLERANCING PER
A1
ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS.
Q A
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
MILLIMETERS PIN 4 DIM MIN MAX BACKSIDE TAB A
2.40 3.00
A1
1.00 1.50
b
0.60 0.90
D b2
0.51 0.88
c
0.39 0.63
P D
10.60 11.10
E
7.40 7.80
1 2 3 e
2.04 2.54
L
14.50 16.63
L1
1.27 2.54
P
2.90 3.30
Q
3.80 4.20
L1 GENERIC L MARKING DIAGRAM*
YWW XX XXXXXG
2X b2
Y = Year WW = Work Week XXXXX = Device Code
2X e b c
G = Pb−Free Package *This information is generic. Please refer to
FRONT VIEW SIDE VIEW
device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1. EMITTER PIN 1. CATHODE PIN 1. BASE PIN 1. ANODE 1 PIN 1. MT 1 2., 4. COLLECTOR 2., 4. ANODE 2., 4. COLLECTOR 2., 4. ANODE 2 2., 4. MT 2 3. BASE 3. GATE 3. EMITTER 3. GATE 3. GATE STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: PIN 1. CATHODE PIN 1. MT 1 PIN 1. SOURCE PIN 1. GATE PIN 1. SOURCE 2., 4. GATE 2., 4. GATE 2., 4. GATE 2., 4. DRAIN 2., 4. DRAIN 3. ANODE 3. MT 2 3. DRAIN 3. SOURCE 3. GATE
DOCUMENT NUMBER: 98ASB42049B
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TO−225 PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
PACKAGE DIMENSIONS TO−225
CASE 77−09 4 ISSUE AD DATE 25 MAR 2015 1 2 3 3 2 1
FRONT VIEW BACK VIEW SCALE 1:1 E
NOTES: 1. DIMENSIONING AND TOLERANCING PER
A1
ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS.
Q A
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
MILLIMETERS PIN 4 DIM MIN MAX BACKSIDE TAB A
2.40 3.00
A1
1.00 1.50
b
0.60 0.90
D b2
0.51 0.88
c
0.39 0.63
P D
10.60 11.10
E
7.40 7.80
1 2 3 e
2.04 2.54
L
14.50 16.63
L1
1.27 2.54
P
2.90 3.30
Q
3.80 4.20
L1 GENERIC L MARKING DIAGRAM*
YWW XX XXXXXG
2X b2
Y = Year WW = Work Week XXXXX = Device Code
2X e b c
G = Pb−Free Package *This information is generic. Please refer to
FRONT VIEW SIDE VIEW
device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1. EMITTER PIN 1. CATHODE PIN 1. BASE PIN 1. ANODE 1 PIN 1. MT 1 2., 4. COLLECTOR 2., 4. ANODE 2., 4. COLLECTOR 2., 4. ANODE 2 2., 4. MT 2 3. BASE 3. GATE 3. EMITTER 3. GATE 3. GATE STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: PIN 1. CATHODE PIN 1. MT 1 PIN 1. SOURCE PIN 1. GATE PIN 1. SOURCE 2., 4. GATE 2., 4. GATE 2., 4. GATE 2., 4. DRAIN 2., 4. DRAIN 3. ANODE 3. MT 2 3. DRAIN 3. SOURCE 3. GATE
DOCUMENT NUMBER: 98ASB42049B
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TO−225 PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com