Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 2

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ADSP-BF700/701/702/703/704/705/706/707 TABLE OF CONTENTS
Features . 1 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal  Peripherals Features . 1 Descriptions . 30 Memory . 1 GPIO Multiplexing for 12 mm × 12 mm 88-Lead  LFCSP (QFN) . 35 Table of Contents . 2 ADSP-BF70x Designer Quick Reference . 37 Revision History . 2 Specifications . 49 General Description . 3 Operating Conditions . 49 Blackfin+ Processor Core . 4 Electrical Characteristics . 52 Instruction Set Description . 5 HADC . 57 Processor Infrastructure . 5 Absolute Maximum Ratings . 57 Memory Architecture . 7 ESD Sensitivity . 57 Security Features . 8 Timing Specifications . 58 Security Features Disclaimer . 8 Output Drive Currents . 100 Processor Safety Features . 9 Test Conditions . 102 Additional Processor Peripherals . 10 Environmental Conditions . 104 Power and Clock Management . 12 ADSP-BF70x 184-Ball CSP_BGA Ball Assignments  System Debug . 15 (Numerical by Ball Number) . 105 Development Tools . 15 ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN)  Additional Information . 16 Lead Assignments (Numerical by Lead Number) . 108 Related Signal Chains . 16 Outline Dimensions . 111 ADSP-BF70x Detailed Signal Descriptions . 17 Surface-Mount Design . 112 184-Ball CSP_BGA Signal Descriptions . 21 Automotive Products . 113 GPIO Multiplexing for 184-Ball CSP_BGA . 28 Ordering Guide . 114
REVISION HISTORY 2/2019—Rev. C to Rev. D
Deleted Package Information (Figure 7 and Table 27) in Specifications . 49 Changes to  TWI0VSEL Settings and VDD_EXT/VBUSTWI . 50 Changes to Test Conditions . 102 Changes to Output Enable Time Measurement . 102 Changes to Output Disable Time Measurement . 102 Changes to Output Enable/Disable . 102 Changes to Automotive Products . 113 Rev. D | Page 2 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide