Datasheet AD5749 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | Industrial Current Out Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges |
| Seiten / Seite | 28 / 2 — AD5749. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 9/2020—Rev. D to … |
| Revision | E |
| Dateiformat / Größe | PDF / 399 Kb |
| Dokumentensprache | Englisch |
AD5749. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 9/2020—Rev. D to Rev. E. 3/2017—Rev. B to Rev. C. 1/2018—Rev. C to Rev. D
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AD5749 Data Sheet TABLE OF CONTENTS
Features .. 1 OUTEN .. 18 Applications ... 1 Software Control .. 18 Functional Block Diagram .. 1 Hardware Control .. 21 General Description ... 1 Transfer Function ... 21 Revision History ... 2 Detailed Description of Features .. 22 Specifications ... 3 Output Fault Alert—Software Mode ... 22 Timing Characteristics .. 5 Output Fault Alert—Hardware Mode ... 22 Absolute Maximum Ratings .. 7 Asynchronous Clear (CLEAR) ... 22 ESD Caution .. 7 External Current Setting Resistor .. 22 Pin Configuration and Function Descriptions ... 8 Programmable Overrange Modes .. 22 Typical Performance Characteristics ... 10 Packet Error Checking ... 23 Terminology .. 15 Applications Information .. 24 Theory of Operation .. 16 Transient Voltage Protection .. 24 Software Mode .. 16 Thermal Considerations .. 24 Current Output Architecture .. 18 Layout Guidelines... 25 Driving Inductive Loads .. 18 Galvanically Isolated Interface ... 25 Power-On State of the AD5749 .. 18 Microprocessor Interfacing ... 25 Default Registers at Power-On ... 18 Outline Dimensions ... 26 Reset Function .. 18 Ordering Guide .. 26
REVISION HISTORY 9/2020—Rev. D to Rev. E 3/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 .. Throughout Changed CP-32-2 to CP-32-7 .. Throughout Changes to Figure 4 .. 8 Changes to Figure 4 ... 8 Updates Outline Dimensions .. 26 Changes to Theory of Operation Section.. 16 Changes to Ordering Guide .. 26 Updated Outline Dimensions ... 26 Changes to Ordering Guide .. 26
1/2018—Rev. C to Rev. D
Changed CP-32-7 to CP-32-2 .. Throughout
10/2013—Rev. A to Rev. B
Changes to Figure 1 .. 1 Changes to Table 4 ... 7 Changed FAULT, IFAULT, TEMP, VFAULT Parameter to Changes to Thermal Considerations Section and Table 12 .. 24 FAULT, IFAULT, TEMP Parameter; Table 2 ... 4 Updated Outline Dimensions ... 26 Changes to Figure 4 and Table 5 ... 8 Updates Outline Dimensions .. 26
7/2012—Rev. 0 to Rev. A
Changes to Ordering Guide .. 26 Changes to Figure 3 ... 6 Changes to Status Bit Read Operation Section... 21 Updated Outline Dimensions ... 26
7/2010—Revision 0: Initial Version
Rev. E | Page 2 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE
AD5749 Data Sheet TABLE OF CONTENTS
Features .. 1 OUTEN .. 18 Applications ... 1 Software Control .. 18 Functional Block Diagram .. 1 Hardware Control .. 21 General Description ... 1 Transfer Function ... 21 Revision History ... 2 Detailed Description of Features .. 22 Specifications ... 3 Output Fault Alert—Software Mode ... 22 Timing Characteristics .. 5 Output Fault Alert—Hardware Mode ... 22 Absolute Maximum Ratings .. 7 Asynchronous Clear (CLEAR) ... 22 ESD Caution .. 7 External Current Setting Resistor .. 22 Pin Configuration and Function Descriptions ... 8 Programmable Overrange Modes .. 22 Typical Performance Characteristics ... 10 Packet Error Checking ... 23 Terminology .. 15 Applications Information .. 24 Theory of Operation .. 16 Transient Voltage Protection .. 24 Software Mode .. 16 Thermal Considerations .. 24 Current Output Architecture .. 18 Layout Guidelines... 25 Driving Inductive Loads .. 18 Galvanically Isolated Interface ... 25 Power-On State of the AD5749 .. 18 Microprocessor Interfacing ... 25 Default Registers at Power-On ... 18 Outline Dimensions ... 26 Reset Function .. 18 Ordering Guide .. 26
REVISION HISTORY 9/2020—Rev. D to Rev. E 3/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 .. Throughout Changed CP-32-2 to CP-32-7 .. Throughout Changes to Figure 4 .. 8 Changes to Figure 4 ... 8 Updates Outline Dimensions .. 26 Changes to Theory of Operation Section.. 16 Changes to Ordering Guide .. 26 Updated Outline Dimensions ... 26 Changes to Ordering Guide .. 26
1/2018—Rev. C to Rev. D
Changed CP-32-7 to CP-32-2 .. Throughout
10/2013—Rev. A to Rev. B
Changes to Figure 1 .. 1 Changes to Table 4 ... 7 Changed FAULT, IFAULT, TEMP, VFAULT Parameter to Changes to Thermal Considerations Section and Table 12 .. 24 FAULT, IFAULT, TEMP Parameter; Table 2 ... 4 Updated Outline Dimensions ... 26 Changes to Figure 4 and Table 5 ... 8 Updates Outline Dimensions .. 26
7/2012—Rev. 0 to Rev. A
Changes to Ordering Guide .. 26 Changes to Figure 3 ... 6 Changes to Status Bit Read Operation Section... 21 Updated Outline Dimensions ... 26
7/2010—Revision 0: Initial Version
Rev. E | Page 2 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE