Datasheet AD8324 (Analog Devices) - 10

AD8324 Data Sheet 180 110 Hz) f = 10MHz / ) 160 100 TXEN = 1 -p (nV p 90 E V 140 m ( S 80 NOIS 120 NT IE 70 100 LTAGE 60 O RANS T 80 50 D V T DOCSIS 2.0 BETWEEN BURST RS TRANSIENT SPECIFICATION RRE 40 60 FE N BU E 30 40 E AD8324 UT RE W 20 T 20 BE 10
-021 0
OUTP
39-
0
04339-0-019
0
043
0 6 12 18 24 30 36 42 48 54 60 0 6 12 18 24 30 36 42 48 54 60 GAIN CONTROL (Decimal Code) GAIN CONTROL (Decimal Code)
Figure 19. Output Referred Voltage Noise vs. Gain Control Figure 21. Between Burst Transient vs. Gain Control
210 190 TA = 25°C 170 NT (mA) 150 CURRE 130 LY P P 110 U T S N 90 E C S 70 QUIE 50 30
04339-0-020
0 6 12 18 24 30 36 42 48 54 60 GAIN CONTROL (Decimal Code)
Figure 20. Quiescent Supply Current vs. Gain Control Rev. C | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE