Datasheet AD8312 (Analog Devices) - 7

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Data Sheet AD8312 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8312 VPOS 1 6 RFIN VOUT 2 5 COMM VSET 3 4 CFLT TOP VIEW (Not to Scale)
05260-002 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Ball No. Mnemonic Description
1 VPOS Positive Supply Voltage (VS), 2.7 V to 5.5 V. 2 VOUT Logarithmic Output. Output voltage increases with increasing input amplitude. 3 VSET Setpoint Input. Connect VSET to VOUT for measurement mode operation. The nominal logarithmic slope of 20 mV/dB can be increased to an arbitrarily high value by attenuating the signal between VOUT and VSET (see the Increasing the Logarithmic Slope section). 4 CFLT Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between CFLT and VOUT. 5 COMM Device Common (Ground). 6 RFIN RF Input. Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL DESCRIPTION APPLICATIONS INFORMATION BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT Filter Capacitor Input Coupling Options Increasing the Logarithmic Slope Effect of Waveform Type on Intercept Temperature Drift Operation Above 2.5 GHz Device Handling Evaluation Board OUTLINE DIMENSIONS ORDERING GUIDE