Datasheet HMC1099PM5E (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 10 W (40 dBm), 0.01 GHz to 1.1 GHz, GaN Power Amplifier |
| Seiten / Seite | 18 / 6 — HMC1099PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND … |
| Revision | B |
| Dateiformat / Größe | PDF / 326 Kb |
| Dokumentensprache | Englisch |
HMC1099PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. 24 GND. NIC 2. 23 NIC. NIC 3. 22 NIC. RFIN/V. 21 RFOUT/V
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HMC1099PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C C ND ND G NI NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC RFIN/V 4 HMC1099PM5E 21 RFOUT/V GG DD RFIN/VGG 5 TOP VIEW 20 RFOUT/VDD NIC (Not to Scale) 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C C C C C ND NI NI NI NI NI NI ND G G NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 2. NO INTERNAL CONNECTION. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER,
002
ALL DATA WAS MEASURED WITH THESE PINS CONNECTED TO RF AND DC GROUND EXTERNALLY.
16826- Figure 2. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data was measured 19, 22, 23, 26 to 31 with these pins connected to RF and dc ground externally. 4, 5 RFIN/VGG RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 49. See Figure 4 for the RFIN/VGG interface schematic. 20, 21 RFOUT/VDD RF Output/Supply Voltage. This pin is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires external matching to 50 Ω, as shown in Figure 49. See Figure 4 for the RFOUT/VDD interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 16826- 16826- Figure 3. GND Interface Figure 4. RFIN/VGG and RFOUT/VDD Interface Rev. B | Page 6 of 18 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Total Quiescent Current by VDD Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Evaluation PCB Outline Dimensions Ordering Guide
HMC1099PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C C ND ND G NI NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC RFIN/V 4 HMC1099PM5E 21 RFOUT/V GG DD RFIN/VGG 5 TOP VIEW 20 RFOUT/VDD NIC (Not to Scale) 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C C C C C ND NI NI NI NI NI NI ND G G NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 2. NO INTERNAL CONNECTION. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER,
002
ALL DATA WAS MEASURED WITH THESE PINS CONNECTED TO RF AND DC GROUND EXTERNALLY.
16826- Figure 2. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data was measured 19, 22, 23, 26 to 31 with these pins connected to RF and dc ground externally. 4, 5 RFIN/VGG RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 49. See Figure 4 for the RFIN/VGG interface schematic. 20, 21 RFOUT/VDD RF Output/Supply Voltage. This pin is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires external matching to 50 Ω, as shown in Figure 49. See Figure 4 for the RFOUT/VDD interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 16826- 16826- Figure 3. GND Interface Figure 4. RFIN/VGG and RFOUT/VDD Interface Rev. B | Page 6 of 18 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Total Quiescent Current by VDD Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Evaluation PCB Outline Dimensions Ordering Guide