Datasheet HMC637BPM5E (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | GaAs, pHEMT, MMIC, Single Positive Supply, DC to 7.5 GHz, 1 W Power Amplifier |
| Seiten / Seite | 21 / 5 — Data Sheet. HMC637BPM5E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | A |
| Dateiformat / Größe | PDF / 691 Kb |
| Dokumentensprache | Englisch |
Data Sheet. HMC637BPM5E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. ACG. GND 1. 24 GND. GG2. 23 NIC. NIC 3. 22 GND. GND 4. 21 RFOUT/VDD
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Data Sheet HMC637BPM5E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C C C ND ND G NI ACG ACG NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND V 2 GG2 23 NIC NIC 3 22 GND GND 4 HMC637BPM5E 21 RFOUT/VDD RFIN 5 TOP VIEW 20 GND (Not to Scale) GND 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 1 1 10 12 13 14 15 16 C C C 1 C 3 ND NI NI NI NI ND G GGV G ACG NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE
002
CONNECTED TO RF/DC GROUND. 2. NIC = NOT INTERNALLY CONNECTED.
16273- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 6, 8, 9, 16, 17, GND Ground. These pins and the exposed pad must be connected to RF/dc ground. 20, 22, 24, 25, 32 2 VGG2 Gate Control 2 for the Amplifier. VGG2 is left open for self biased mode. Adjusting the voltage controls the gain response. External capacitors are required (see Figure 70). See Figure 7 for the interface schematic. 3, 7, 10 to 12, 14, NIC Not Internally Connected. These pins must be connected to RF/dc ground. 18, 19, 23, 26 to 28, 31 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 13 VGG1 Optional Gate Control for the Amplifier. If this pin is grounded, the amplifier runs in self biased mode at the standard current of 345 mA. Adjusting the voltage above or below the ground potential controls the drain current. External capacitors are required (see Figure 70). See Figure 8 for the interface schematic. 15, 29, 30 ACG1, ACG2, Low Frequency Termination. External bypass capacitors are required on these pins (see Figure 70). See ACG3 Figure 4 and Figure 5 for the interface schematics. 21 RFOUT/VDD RF Output for the Amplifier (RFOUT). Drain Bias Voltage (VDD). Connect the dc bias (VDD) network to provide the drain current, IDD (see Figure 70). See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. A | Page 5 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS FREQUENCY RANGE = DC TO 7.5 GHz ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet HMC637BPM5E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C C C ND ND G NI ACG ACG NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND V 2 GG2 23 NIC NIC 3 22 GND GND 4 HMC637BPM5E 21 RFOUT/VDD RFIN 5 TOP VIEW 20 GND (Not to Scale) GND 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 1 1 10 12 13 14 15 16 C C C 1 C 3 ND NI NI NI NI ND G GGV G ACG NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE
002
CONNECTED TO RF/DC GROUND. 2. NIC = NOT INTERNALLY CONNECTED.
16273- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 6, 8, 9, 16, 17, GND Ground. These pins and the exposed pad must be connected to RF/dc ground. 20, 22, 24, 25, 32 2 VGG2 Gate Control 2 for the Amplifier. VGG2 is left open for self biased mode. Adjusting the voltage controls the gain response. External capacitors are required (see Figure 70). See Figure 7 for the interface schematic. 3, 7, 10 to 12, 14, NIC Not Internally Connected. These pins must be connected to RF/dc ground. 18, 19, 23, 26 to 28, 31 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 13 VGG1 Optional Gate Control for the Amplifier. If this pin is grounded, the amplifier runs in self biased mode at the standard current of 345 mA. Adjusting the voltage above or below the ground potential controls the drain current. External capacitors are required (see Figure 70). See Figure 8 for the interface schematic. 15, 29, 30 ACG1, ACG2, Low Frequency Termination. External bypass capacitors are required on these pins (see Figure 70). See ACG3 Figure 4 and Figure 5 for the interface schematics. 21 RFOUT/VDD RF Output for the Amplifier (RFOUT). Drain Bias Voltage (VDD). Connect the dc bias (VDD) network to provide the drain current, IDD (see Figure 70). See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. A | Page 5 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS FREQUENCY RANGE = DC TO 7.5 GHz ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE