ADPA7002Data SheetTYPICAL PERFORMANCE CHARACTERISTICS20201518B)1610d ( S14S5O120B) dURN L TS11N (10–5S21AI, RES22G8B) d–10N (6AI G–154–202–25014 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 010 013 1820222426283032343638404244FREQUENCY (GHz) 20071- FREQUENCY (GHz) 20071- Figure 10. Gain and Return Loss vs. Frequency Figure 13. Gain vs. Frequency for Various Temperatures 2020181816164V145V141212B)B)ddN (10N (10AIAIG8G866600mA44700mA 800mA22 1 0 1 0 0 1820222426283032343638404244 014 1820222426283032343638404244 20071- FREQUENCY (GHz)FREQUENCY (GHz) 20071- Figure 11. Gain vs. Frequency for Various Drain Voltages Figure 14. Gain vs. Frequency for Various Quiescent Drain Currents 00+85°C4V+25°C5V–40°C–5–5B)B)dd((SSSSO–10O–10URN LURN LTT–15–15REREUTUTINPINP–20–20–25–25 012 18202224262830323436384042441820222426283032343638404244 015 FREQUENCY (GHz)FREQUENCY (GHz) 20071- 20071- Figure 12. Input Return Loss vs. Frequency for Various Temperatures, Figure 15. Input Return Loss vs. Frequency for Various Drain Voltages VDD = 5 V, IDQ = 700 mA Rev. 0 | Page 8 of 21 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications 18 GHz to 20 GHz Frequency Range 20 GHz to 24 GHz Frequency Range 24 GHz to 34 GHz Frequency Range 34 GHz to 44 GHz Frequency Range Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Constant IDD Operation Theory of Operation Applications Information Biasing Procedures Biasing the ADPA7002 with the HMC980LP4E Application Circuit Setup Limiting VGATE to Meet the ADPA7002 VGG1 AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Biasing vs. Constant Gate Voltage Biasing Testing the HMC980LP4E Outline Dimensions Ordering Guide