Datasheet ADPA7004CHIPS (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 40 GHz to 80 GHz, GaAs, pHEMT, MMIC, Wideband Power Amplifier |
| Seiten / Seite | 20 / 6 — ADPA7004CHIPS. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Dateiformat / Größe | PDF / 465 Kb |
| Dokumentensprache | Englisch |
ADPA7004CHIPS. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 1234. RFOUT. TOP VIEW. (Not to Scale). RFIN. 1234B
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ADPA7004CHIPS Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A 1234 A A A A 1 2 3 1234 4 GG DD DD DD GG DD V V V V V V 2 3 4 5 6 7 8 RFOUT ADPA7004CHIPS TOP VIEW (Not to Scale) RFIN 1 16 15 14 13 12 11 10 9 F T 1B 2B 3B 4B RE DE DD V V 1234B DD DD DD V V V 1234B V
002
GG GG V V
23893- Figure 2. Pad Configuration
Table 7. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2, 6 VGG1234A Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. 3, 4, 5, 7 VDD1A, VDD2A, VDD3A, VDD4A Top Edge Drain Bias Voltage Pads for the Amplifiers. External bypass capacitors are required on the VDD1A, VDD2A, VDD3A, and VDD4A pads. Connect the VDD1A, VDD2A, VDD3A, and VDD4A pads to a 3.5 V supply. See Figure 5 for the interface schematic. 8 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic. 9 VDET DC Voltage Representing the RF Output Power. The voltage is rectified by the diode that is biased through external resistor. See Figure 9 for the interface schematic. 10 VREF Reference DC Voltage for the Temperature Compensation of the VDET diode. See Figure 10 for the interface schematic. 11, 13, 14, 15 VDD4B, VDD3B, VDD2B, VDD1B Bottom Edge Drain Bias Voltage Pads for Amplifiers. External bypass capacitors are required on the VDD4B, VDD3B, VDD2B, and VDD1B pads. Connect the VDD4B, VDD3B, VDD2B, and VDD1B pads to a 3.5 V supply. See Figure 7 for the interface schematic. 12, 16 VGG1234B Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers, Alternative Bias Configuration. See Figure 8 for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF and dc ground. See Figure 6 for the interface schematic. Rev. 0 | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 40 GHz TO 45 GHz FREQUENCY RANGE 45 GHz TO 75 GHz FREQUENCY RANGE 75 GHz TO 80 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings ADPA7004CHIPS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION POWER-UP AND POWER-DOWN SEQUENCING Power-Up Sequence Power-Down Sequence RF DETECTOR OPERATION ASSEMBLY DIAGRAM MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE
ADPA7004CHIPS Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A 1234 A A A A 1 2 3 1234 4 GG DD DD DD GG DD V V V V V V 2 3 4 5 6 7 8 RFOUT ADPA7004CHIPS TOP VIEW (Not to Scale) RFIN 1 16 15 14 13 12 11 10 9 F T 1B 2B 3B 4B RE DE DD V V 1234B DD DD DD V V V 1234B V
002
GG GG V V
23893- Figure 2. Pad Configuration
Table 7. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2, 6 VGG1234A Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. 3, 4, 5, 7 VDD1A, VDD2A, VDD3A, VDD4A Top Edge Drain Bias Voltage Pads for the Amplifiers. External bypass capacitors are required on the VDD1A, VDD2A, VDD3A, and VDD4A pads. Connect the VDD1A, VDD2A, VDD3A, and VDD4A pads to a 3.5 V supply. See Figure 5 for the interface schematic. 8 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic. 9 VDET DC Voltage Representing the RF Output Power. The voltage is rectified by the diode that is biased through external resistor. See Figure 9 for the interface schematic. 10 VREF Reference DC Voltage for the Temperature Compensation of the VDET diode. See Figure 10 for the interface schematic. 11, 13, 14, 15 VDD4B, VDD3B, VDD2B, VDD1B Bottom Edge Drain Bias Voltage Pads for Amplifiers. External bypass capacitors are required on the VDD4B, VDD3B, VDD2B, and VDD1B pads. Connect the VDD4B, VDD3B, VDD2B, and VDD1B pads to a 3.5 V supply. See Figure 7 for the interface schematic. 12, 16 VGG1234B Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers, Alternative Bias Configuration. See Figure 8 for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF and dc ground. See Figure 6 for the interface schematic. Rev. 0 | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 40 GHz TO 45 GHz FREQUENCY RANGE 45 GHz TO 75 GHz FREQUENCY RANGE 75 GHz TO 80 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings ADPA7004CHIPS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION POWER-UP AND POWER-DOWN SEQUENCING Power-Up Sequence Power-Down Sequence RF DETECTOR OPERATION ASSEMBLY DIAGRAM MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE