Datasheet ADPA1105 (Analog Devices) - 5

link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5
Data Sheet ADPA1105 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D DD1 DD2 GN V NC NC V NC NC GN 32 31 30 29 28 27 26 25 GND 1 24 GND NC 2 23 NC NC 3 22 NC ADPA1105 RFIN 4 21 RFOUT RFIN 5 TOP VIEW 20 RFOUT (Not to Scale) GND 6 19 GND NC 7 18 NC GND 8 17 GND 9 10 11 12 13 14 15 16 D D NC NC ET EF GN GG1 GG2 V V VD VR GN NOTES 1. THE NC PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA SHOWN IS MEASURED WITH THE NC PINS CONNECTED TO RF AND DC GROUND EXTERNALLY. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE
002
CONNECTED TO RF AND DC GROUND.
25- 19 2 Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 6, 8, 9, 16, 17, 19, GND The GND pins must be connected to RF and dc ground. See Figure 6 for the interface schematic. 24, 25, 32 2, 3, 7, 12, 13, 18, 22, NC The NC pins are not connected internally. However, all data shown is measured with the NC pins 23, 26, 27, 29, 30 connected to RF and dc ground externally. 4, 5 RFIN RF Input. The RFIN pins are ac-coupled and are matched to 50 Ω. See Figure 3 for the interface schematic. 10 VGG1 Gate Control, First Stage Gate Bias. See Figure 3 for the interface schematic. 11 VGG2 Gate Control, Second Stage Gate Bias. See Figure 4 for the interface schematic. 14 VDET Detector Diode to Measure RF Output Power. Output power detection via VDET requires the application of a dc bias voltage through an external series resistor. Used in combination with the VREF pin, the difference in voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to the RF output power. 15 VREF Reference Diode for Temperature Compensation of VDET RF Output Power Measurements. VREF requires the application of a dc bias voltage through an external series resistor. 20, 21 RFOUT RF Output. The RFOUT pins are ac-coupled and are matched to 50 Ω. See Figure 4 for the interface schematic. 28 VDD2 Amplifier Power Supply Voltage, Second Stage Drain Bias. See Figure 4 for the interface schematic. 31 VDD1 Amplifier Power Supply Voltage, First Stage Drain Bias. See Figure 3 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS VDD1 RFIN
005 5- 003 5-
VREF
2192
VGG1
2192 Figure 3. RFIN, V Figure 5. VREF Interface GG1, and VDD1 Interface
VDD2 RFOUT GND
004 06
V
5- 0
GG2
5- 92
VDET
2192 21 Figure 4. RFOUT, V Figure 6. GND Interface GG2, VDD2, and VDET Interface Rev. 0 | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADPA1105 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS THERMAL MANAGEMENT OUTLINE DIMENSIONS ORDERING GUIDE