link to page 19 link to page 19 link to page 19 link to page 19 Data SheetADL8111065IN_B TO RFOUT, +85°C60–10IN_B TO RFOUT, +25°C IN_B TO RFOUT, –40°C55–205045)–30dB40(Bm)35–40dTION3 (30OLAIIP–5025+85°CIS+25°C20–40°C–601510–705–800012345678 024 012345678 026 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 22. Isolation vs. Frequency Over Temperature, Figure 24. IIP3 vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 4040363632322828+85°C+85°C24+25°C24+25°C–40°CBm)–40°CBm)dd2020B (B (1d5d16P160. P1212884400012345678 025 012345678 027 FREQUENCY (GHz)FREQUENCY (GHz) 20106- 20106- Figure 23. P0.5dB vs. Frequency Over Temperature, Figure 25. P1dB Compression vs. Frequency Over Temperature, State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Figure 75 for the Test Circuit) Rev. 0 | Page 9 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE