Datasheet ADL8111 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 10 MHz to 8000 MHz Bypass Amplifier |
| Seiten / Seite | 24 / 6 — ADL8111. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. IN_A. … |
| Dateiformat / Größe | PDF / 811 Kb |
| Dokumentensprache | Englisch |
ADL8111. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. IN_A. 23 22. VDD_PA. GND. VBIAS. RFIN. RFOUT. TOP VIEW. (Not to Scale)
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ADL8111 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS _A ND UT ND ND ND ND G O G G G IN_A G 28 27 26 25 24 23 22 VDD_PA 1 21 GND VBIAS 2 ADL8111 20 GND GND 3 19 GND GND GND RFIN 4 18 RFOUT GND TOP VIEW 5 17 GND (Not to Scale) VA 6 16 VDD_SW GND GND VB 7 15 VSS_SW 8 9 10 11 12 13 14 ND _B ND ND ND ND G UT G G G IN_B G O NOTES
005
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
20106- Figure 5. Pin Configuration—Top View Not to Scale
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD_PA Drain Bias Voltage. See Table 2. 2 VBIAS Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external resistor. See Figure 9 for the interface schematic. 3, 5, 8, 10 to 12, 14, 17, 19 to GND RF and DC Ground. See Figure 6 for the interface schematic. 22, 24 to 26, 28 4 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 6, 7 VA, VB Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface schematics. 9, 13 OUT_B, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF IN_B line potential is not equal to 0 V dc. 15 VSS_SW Negative Bias Voltage. See Table 2. 16 VDD_SW Positive Bias Voltage. See Table 2. 18 RFOUT RF Output. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 23, 27 IN_A, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF OUT_A line potential is not equal to 0 V dc. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS VDD_SW GND VA
008 006 20106- 20106- Figure 6. GND Interface Schematic Figure 8. VA Interface Schematic
VBIAS VDD_SW VB
007 20106- 109 20106- Figure 7. VB Interface Schematic Figure 9. VBIAS Interface Schematic Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE
ADL8111 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS _A ND UT ND ND ND ND G O G G G IN_A G 28 27 26 25 24 23 22 VDD_PA 1 21 GND VBIAS 2 ADL8111 20 GND GND 3 19 GND GND GND RFIN 4 18 RFOUT GND TOP VIEW 5 17 GND (Not to Scale) VA 6 16 VDD_SW GND GND VB 7 15 VSS_SW 8 9 10 11 12 13 14 ND _B ND ND ND ND G UT G G G IN_B G O NOTES
005
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
20106- Figure 5. Pin Configuration—Top View Not to Scale
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD_PA Drain Bias Voltage. See Table 2. 2 VBIAS Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external resistor. See Figure 9 for the interface schematic. 3, 5, 8, 10 to 12, 14, 17, 19 to GND RF and DC Ground. See Figure 6 for the interface schematic. 22, 24 to 26, 28 4 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 6, 7 VA, VB Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface schematics. 9, 13 OUT_B, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF IN_B line potential is not equal to 0 V dc. 15 VSS_SW Negative Bias Voltage. See Table 2. 16 VDD_SW Positive Bias Voltage. See Table 2. 18 RFOUT RF Output. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 23, 27 IN_A, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF OUT_A line potential is not equal to 0 V dc. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS VDD_SW GND VA
008 006 20106- 20106- Figure 6. GND Interface Schematic Figure 8. VA Interface Schematic
VBIAS VDD_SW VB
007 20106- 109 20106- Figure 7. VB Interface Schematic Figure 9. VBIAS Interface Schematic Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE