Datasheet MSMXVHF (MSI) - 4
Hersteller | MSI |
Beschreibung | High Frequency Mixxer and Selecttable VHF LP//BP Filtter |
Seiten / Seite | 7 / 4 — MSMXVHF |
Dateiformat / Größe | PDF / 65 Kb |
Dokumentensprache | Englisch |
MSMXVHF
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Textversion des Dokuments
6/2014 High Frequency Mixer and Selectable VHF LP/BP Filter Data Sheet 2 = Banpass; 0= Lowpass Filter Selection 16. FOUT Filter Output The filter type is selected using the two filter se- Gain and Frequency Selection lect pins, TYPE and FSEL, FSEL is a CMOS level pin that selects lowpass or bandpass The Gain select pin G is a tertiary control pin response (lowpass = 0, bandpass = 2). TYPE Is where state 0 is VSS, state 1 is AGND level a tertiary control pin that selects the filter and state 2 is VDD. response. State 0 is VSS, state 1 is AGND and state 2 is VDD. G Gain 0 OdB TYPE Lowpass Bandpass 1 10dB 0 Butterworth Full Octave 2 20dB 1 Bessel Third Octave 2 Elliptic Sixth Octave The clock to corner select pin F0 is a CMOS level pin where HIGH is clock to corner of 12.5 Pin Description to 1 (25 to 1 for Bessel) and LOW is clock to corner of 6.25 to 1 (12.5 to 1 for Bessel). The 1. TYPE Filter Response Select Pin. sample rate ratio is twice the clock to corner
MSMXVHF
2. FCLK Filter Clock Input ratio (double sampling). 3. G Gain Select Pin 4. PWR Power Select Pin; CMOS level Pin Configuration High= Regular Power; Low=Low Power 5. VDD Positive Power Supply,Typically TYPE +1.5 Volts for Split Supply, +3.0 1 16 FOUT Volts for Single Supply 6. PDown Power Down Pin, CMOS level, FCLK 2 15 FSEL Hi = Power Down 7, VSS Negative Power Supply,Typically G 3 14 MIX1 -1.5 Volts for Split Supply, 0 Volts for Single Supply PWR 4 13 MIX2 8. MCLK Mixer Clock: CMOS Levels 9. F0 Clock to Corner Select Pin VDD 5 12 FIN 10. MO Mixer Output 11. AGND GND Pin, OV for Split Supplies PD 11 AGND +1.5 Volts Typical for Single 6 Supply 12. FIN Filter Input VSS 7 10 MO 13. MIX2 Mixer Input 2 14. MIX1 Mixer Input 1 MCLK 8 9 FO 15. FSEL Filter Select Web Site “www.mix-ssig.com” ©2011-2 2014 Mixed Signal Integration 4