Datasheet BUK9V13-40H (Nexperia)
| Hersteller | Nexperia |
| Beschreibung | Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) |
| Seiten / Seite | 13 / 1 — BUK9V13-40H. Dual N-channel 40 V, 13 mOhm logic level MOSFET in. LFPAK56D … |
| Revision | 11022021 |
| Dateiformat / Größe | PDF / 313 Kb |
| Dokumentensprache | Englisch |
BUK9V13-40H. Dual N-channel 40 V, 13 mOhm logic level MOSFET in. LFPAK56D (half-bridge configuration). 11 February 2021
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BUK9V13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 11 February 2021 Product data sheet 1. General description
Dual, logic level N-channel MOSFET in an LFPAK56D package D1 (half-bridge configuration), using Trench 9 TrenchMOS technology. This product has been designed and qualified to AEC-Q101. G1 An internal connection is made between the source (S1) of the high- S1, D2 side FET to the drain (D2) of the low-side FET, making the device ideal to use as a half-bridge switch in high-performance automotive PWM G2 applications. S2 aaa-028081
2. Features and benefits
• LFPAK56D package with half-bridge configuration enables: • Reduced PCB layout complexity • PCB shrinkage through reduced component footprint for 3-phase motor drive • Improved system level Rth(j-amb) due to optimized package design • Lower parasitic inductance to support higher ef iciency • Footprint compatibility with LFPAK56D Dual package • Advanced AEC-Q101 grade Trench 9 silicon technology: • Low power losses, high power density • Superior avalanche performance • Repetitive avalanche rated • LFPAK copper clip packaging provides high robustness and reliability • Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
3. Applications
• 12 V automotive systems • Powertrain, chassis, body and infotainment applications • Brushless or brushed DC motor drive • DC-to-DC systems • LED lighting
4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Limiting values FET1 and FET2
VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - - 42 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 46 W Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents
BUK9V13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 11 February 2021 Product data sheet 1. General description
Dual, logic level N-channel MOSFET in an LFPAK56D package D1 (half-bridge configuration), using Trench 9 TrenchMOS technology. This product has been designed and qualified to AEC-Q101. G1 An internal connection is made between the source (S1) of the high- S1, D2 side FET to the drain (D2) of the low-side FET, making the device ideal to use as a half-bridge switch in high-performance automotive PWM G2 applications. S2 aaa-028081
2. Features and benefits
• LFPAK56D package with half-bridge configuration enables: • Reduced PCB layout complexity • PCB shrinkage through reduced component footprint for 3-phase motor drive • Improved system level Rth(j-amb) due to optimized package design • Lower parasitic inductance to support higher ef iciency • Footprint compatibility with LFPAK56D Dual package • Advanced AEC-Q101 grade Trench 9 silicon technology: • Low power losses, high power density • Superior avalanche performance • Repetitive avalanche rated • LFPAK copper clip packaging provides high robustness and reliability • Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
3. Applications
• 12 V automotive systems • Powertrain, chassis, body and infotainment applications • Brushless or brushed DC motor drive • DC-to-DC systems • LED lighting
4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Limiting values FET1 and FET2
VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - - 42 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 46 W Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents