Datasheet AD817 (Analog Devices) - 9

AD817 DRIVING CAPACITIVE LOADS +VS
The internal compensation of the AD817, together with its high output current drive, permit excellent large signal performance while driving extremely high capacitive loads.
1k
Ω
OUTPUT 3.3
µ
F +V C S F –IN 0.01
µ
F RIN HP V 1k
Ω
IN 7 PULSE 2 TEKTRONIX TEKTRONIX V GENERATOR OUT P6201 FET 7A24 AD817 6 +IN 50
Ω
PROBE PREAMP 3 4 0.01
µ
F CL 1000pF –V 3.3
µ
F S NULL 1 NULL 8 –VS
Figure 31. Simplified Schematic Figure 30a. Inverting Amplifier Driving a 1000 pF Capacitive Load
INPUT CONSIDERATIONS
An input protection resistor (RIN in Figure 22) is required in cir- cuits where the input to the AD817 will be subjected to tran-
5V 500ns
sient or continuous overload voltages exceeding the +6 V
100
maximum differential limit. This resistor provides protection for
90 100pF
the input transistors by limiting their maximum base current. For high performance circuits, it is recommended that a “bal- ancing” resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of RIN and RF and thus provides a matched impedance at each input
10 1000pF
terminal. The offset voltage error will then be reduced by more
0%
than an order of magnitude.
5V GROUNDING & BYPASSING
When designing high frequency circuits, some special precau- Figure 30b. Inverting Amplifier Pulse Response While tions are in order. Circuits must be built with short interconnect Driving Capacitive Loads leads. When wiring components, care should be taken to pro- vide a low resistance, low inductance path to ground. Sockets
THEORY OF OPERATION
should be avoided, since their increased interlead capacitance The AD817 is a low cost, wide band, high performance opera- can degrade circuit bandwidth. tional amplifier which effectively drives heavy capacitive or resis- tive loads. It also provides a constant slew rate, bandwidth and Feedback resistors should be of low enough value (<1 kΩ) to settling time over its entire specified temperature range. assure that the time constant formed with the inherent stray capacitance at the amplifier’s summing junction will not limit The AD817 (Figure 31) consists of a degenerated NPN differ- performance. This parasitic capacitance, along with the parallel ential pair driving matched PNPs in a folded-cascode gain stage. resistance of RF/RIN, form a pole in the loop transmission which The output buffer stage employs emitter followers in a class AB may result in peaking. A small capacitance (1 pF–5 pF) may be amplifier which delivers the necessary current to the load while used in parallel with the feedback resistor to neutralize this effect. maintaining low levels of distortion. Power supply leads should be bypassed to ground as close as The capacitor, CF, in the output stage mitigates the effect of possible to the amplifier pins. Ceramic disc capacitors of 0.1 µF capacitive loads. At low frequencies, and with low capacitive are recommended. loads, the gain from the compensation node to the output is very close to unity. In this case, C
+V
F is bootstrapped and does not
S
contribute to the overall compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the
2 7
output impedance of the output stage. This reduces the gain,
AD817 6
and therefore, CF is incompletely bootstrapped. Effectively,
8
some fraction of C
3 1
F contributes to the overall compensation
4
capacitance, reducing the unity gain bandwidth. As the load
10k
Ω
V ADJUST OS
capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier.
–VS
Figure 32. Offset Null Configuration REV. B –9–