Datasheet LT8613 (Analog Devices) - 19

LT8613
APPLICATIONS INFORMATION PCB Layout
ISN ISP For proper operation and minimum EMI, care must be taken ICTRL IMON GND during printed circuit board layout. Figure 6 shows the rec- ommended component placement with trace, ground plane 28 27 26 25 and via locations. Note that large, switched currents flow in VOUT SYNC 1 24 FB the LT8613’s VIN pins, PGND pins, and the input capacitor (C1). The loop formed by the input capacitor should be as TR/SS 2 23 PG small as possible by placing the capacitor adjacent to the RT 3 22 BIAS VIN and PGND pins. When using a physically large input EN/UV 4 21 INTVCC capacitor the resulting loop may become too large in which case using a small case/value capacitor placed close to the 5 20 BST VIN VIN and PGND pins plus a larger capacitor further away is 6 19 preferred. These components, along with the inductor and output capacitor, should be placed on the same side of the 7 18 circuit board, and their connections should be made on 8 17 SW that layer. Place a local, unbroken ground plane under the 9 16 application circuit on the layer closest to the surface layer. GND The SW and BOOST nodes should be as small as possible. 10 15 Finally, keep the FB and RT nodes small so that the ground 11 12 13 14 traces will shield them from the SW and BOOST nodes. The exposed pad on the bottom of the package must be soldered to ground so that the pad is connected to ground electrically and also acts as a heat sink thermally. To keep VOUT thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT8613 8613 F06 VOUT LINE TO BIAS LINE TO ISP OUTLINE OF LOCAL to additional ground planes within the circuit board and on VOUT LINE TO ISN VIAS TO GROUND PLANE GROUND PLANE the bottom side.
Figure 6. Recommended PCB Layout for the LT8613 High Temperature Considerations
For higher ambient temperatures, care should be taken in temperature approaches the maximum junction rating. the layout of the PCB to ensure good heat sinking of the Power dissipation within the LT8613 can be estimated by LT8613. The exposed pad on the bottom of the package calculating the total power loss from an efficiency mea- must be soldered to a ground plane. This ground should be surement and subtracting the inductor loss. The die tem- tied to large copper layers below with thermal vias; these perature is calculated by multiplying the LT8613 power layers will spread heat dissipated by the LT8613. Placing dissipation by the thermal resistance from junction to additional vias can reduce thermal resistance further. The ambient. The LT8613 will stop switching and indicate a maximum load current should be derated as the ambient fault condition if safe junction temperature is exceeded. Rev. A For more information www.analog.com 19 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts